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Code Issues Projects Releases Wiki Activity

kernel: qca-ssdk: update to 12.5 for kernel 6.6

Browse Source 
Qualcomm recently committed a new branch (12.5.r2) targeting kernel
6.6. This lets us clean up a few patches particularly the one for
"C22/C45" mdio.

A quick way to see what changed for IPQ807x/6018 was to list the files produced
during build (**/*.o), replace the extension with ".c", and doing a
`git log`.

Filtering from those commits, ones of particular interest are listed
below:

```
2024-04-16 - 0d8f30aa - fix compile issue on hk with linux style build
2024-01-29 - 636464f7 - update the check for port link notify
2024-01-24 - 30c10e7f - enable and disable loopback for xgmac to fix qm stuck issue
2024-01-15 - b6ea10aa - update the the APIs to access switch
2024-01-08 - a1687502 - Disable Tx bridge mac before power off the PHY
2024-01-07 - 3eafb613 - support led configure for malibu phy
2024-01-07 - 5c1af60d - remove phy type check from mac reset when mode switch
2023-12-17 - 79d0b1e8 - remove the PHY access APIs in ssdk_plat.c
2023-12-16 - b2953740 - Update mii read/write functions
2023-12-11 - 37f2eac3 - add port id check for fdb entry
2023-12-11 - d040ca4d - support mdio clause45 on kernel6.6
2023-12-07 - 11494fbc - use barrier mw() during access fdb entry table
2023-12-03 - 8e40a284 - fix build warnings on kernel6.6
2023-11-10 - 10aa0a02 - change speed value when call ssdk_port_link_notify
2023-11-06 - ee4c4a60 - Update mac bitmap value of L3 table on MAC delete
2023-11-03 - 7cd27d39 - support 10G phy common feature
2023-10-30 - 383cc0d2 - fix mactype and mux select issue
2023-10-24 - decf534a - support autoneg status query on force port
2023-10-11 - 111d574e - move ssdk_led_init to regi_init
2023-10-08 - 6b14c142 - the combo port also need to parse SFP pins
2023-10-03 - fb2e0401 - fix port5 interface mode switch issue in erp case
```

Verified with users on QNAP 301W, NBG7815, and myself on Dynalink
DL-WRX36 that everything is functional, including LEDS.

Signed-off-by: Sean Khan <datapronix@protonmail.com>
Link: https://github.com/openwrt/openwrt/pull/15379
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Sean Khan 2024-05-04 17:09:08 -04:00 committed by Robert Marko
parent ce4da3cf41
commit cae1b504e9
7 changed files with 47 additions and 161 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
package/kernel/qca-ssdk/Makefile
View File

@ -1,13 +1,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=qca-ssdk
PKG_RELEASE:=6
PKG_RELEASE:=1
PKG_SOURCE_URL:=https://git.codelinaro.org/clo/qsdk/oss/lklm/qca-ssdk.git
PKG_SOURCE_PROTO:=git
PKG_SOURCE_DATE:=2023-10-04
PKG_SOURCE_VERSION:=23a5aa4a4d5834da7a07efb58baebfbee91786b0
PKG_MIRROR_HASH:=53fb201053b3aca004c4da07b06a0608b0b3322a2062b1f7ab3b3a7871ddabcb
PKG_SOURCE_DATE:=2024-04-17
PKG_SOURCE_VERSION:=3d060f7ad70d087f6b0452abe79ab6d042e8cd53
PKG_MIRROR_HASH:=6f5e390b294e699491584094f5d7eb941de6237ad8c5320191e9e306fbcd8eb5
PKG_FLAGS:=nonshared
PKG_BUILD_PARALLEL:=1

47
package/kernel/qca-ssdk/patches/0001-config-identify-kernel-6.6.patch
View File

@ -1,47 +0,0 @@
From f6c0115daaac586740e873a3b8145c5370a73dce Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Sat, 17 Feb 2024 13:02:31 +0100
Subject: [PATCH] config: identify kernel 6.6
Identify kernel 6.6 so it can be compiled against.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
config | 5 +++++
make/linux_opt.mk | 4 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
--- a/config
+++ b/config
@@ -27,6 +27,11 @@ endif
ifeq ($(KVER),$(filter 6.1%,$(KVER)))
OS_VER=6_1
endif
+
+ifeq ($(KVER),$(filter 6.6%,$(KVER)))
+ OS_VER=6_6
+endif
+
ifeq ($(KVER), 3.4.0)
OS_VER=3_4
endif
--- a/make/linux_opt.mk
+++ b/make/linux_opt.mk
@@ -450,7 +450,7 @@ ifeq (KSLIB, $(MODULE_TYPE))
KASAN_SHADOW_SCALE_SHIFT := 3
endif
- ifeq ($(OS_VER),$(filter 5_4 6_1, $(OS_VER)))
+ ifeq ($(OS_VER),$(filter 5_4 6_1 6_6, $(OS_VER)))
ifeq ($(ARCH), arm64)
KASAN_OPTION += -DKASAN_SHADOW_SCALE_SHIFT=$(KASAN_SHADOW_SCALE_SHIFT)
endif
@@ -481,7 +481,7 @@ ifeq (KSLIB, $(MODULE_TYPE))
endif
- ifeq ($(OS_VER),$(filter 4_4 5_4 6_1, $(OS_VER)))
+ ifeq ($(OS_VER),$(filter 4_4 5_4 6_1 6_6, $(OS_VER)))
MODULE_CFLAG += -DKVER34
MODULE_CFLAG += -DKVER32
MODULE_CFLAG += -DLNX26_22

2
package/kernel/qca-ssdk/patches/101-hsl_phy-add-support-for-detection-PSGMII-PHY-mode.patch
View File

@ -13,7 +13,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
--- a/src/hsl/phy/hsl_phy.c
+++ b/src/hsl/phy/hsl_phy.c
@@ -1335,6 +1335,9 @@ hsl_port_phydev_interface_mode_status_ge
@@ -1322,6 +1322,9 @@ hsl_port_phydev_interface_mode_status_ge
case PHY_INTERFACE_MODE_10GKR:
*interface_mode_status = PORT_10GBASE_R;
break;

16
package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch
View File

@ -24,15 +24,15 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
--- a/include/init/ssdk_dts.h
+++ b/include/init/ssdk_dts.h
@@ -101,6 +101,7 @@ typedef struct
@@ -99,6 +99,7 @@ typedef struct
a_uint32_t emu_chip_ver; /*only valid when is_emulation is true*/
a_uint32_t clk_mode;
a_uint32_t pcie_hw_base;
+ a_uint32_t port3_pcs_channel;
led_ctrl_pattern_t source_pattern[SSDK_MAX_PORT_NUM][PORT_LED_SOURCE_MAX];
} ssdk_dt_cfg;
#define SSDK_MAX_NR_ETH 6
@@ -162,6 +163,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t
@@ -161,6 +162,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t
struct device_node *ssdk_dts_node_get(a_uint32_t dev_id);
struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id);
struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id);
@ -62,7 +62,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
cppe_port_mux_ctrl.bf.port4_pcs_sel =
--- a/src/adpt/hppe/adpt_hppe_uniphy.c
+++ b/src/adpt/hppe/adpt_hppe_uniphy.c
@@ -1122,9 +1122,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
@@ -1160,9 +1160,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
{
a_uint32_t i;
sw_error_t rv = SW_OK;
@ -72,7 +72,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
union uniphy_mode_ctrl_u uniphy_mode_ctrl;
@@ -1134,9 +1131,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
@@ -1172,9 +1169,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index);
#if defined(CPPE)
if (adpt_ppe_type_get(dev_id) == CPPE_TYPE) {
@ -96,10 +96,10 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
+ return cfg->port3_pcs_channel;
+}
+
#ifndef BOARD_AR71XX
#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id,
@@ -306,6 +313,25 @@ static void ssdk_dt_parse_mac_mode(a_uin
struct device_node *switch_node, ssdk_init_cfg *cfg)
@@ -305,6 +312,25 @@ static void ssdk_dt_parse_mac_mode(a_uin
return;
}
@ -125,7 +125,7 @@ Signed-off-by: Mantas Pucka <mantas@8devices.com>
#ifdef IN_UNIPHY
static void ssdk_dt_parse_uniphy(a_uint32_t dev_id)
{
@@ -1292,6 +1318,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg *
@@ -1347,6 +1373,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg *
rv = ssdk_dt_parse_access_mode(switch_node, ssdk_dt_priv);
SW_RTN_ON_ERROR(rv);
ssdk_dt_parse_mac_mode(*dev_id, switch_node, cfg);

98
package/kernel/qca-ssdk/patches/103-mdio-adapt-to-C22-and-C45-read-write-split.patch
View File

@ -1,98 +0,0 @@
From bdae481e89cbe551068a99028bb57119b59f5ff4 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Tue, 26 Mar 2024 12:19:49 +0100
Subject: [PATCH] mdio: adapt to C22 and C45 read/write split
Kernel 6.3 has introduced separate C45 read/write operations, and thus
split them out of the C22 operations completely so the old way of marking
C45 reads and writes via the register value does not work anymore.
This is causing SSDK to fail and find C45 only PHY-s such as Aquantia ones:
[ 22.187877] ssdk_phy_driver_init[371]:INFO:dev_id = 0, phy_adress = 8, phy_id = 0x0 phytype doesn't match
[ 22.209924] ssdk_phy_driver_init[371]:INFO:dev_id = 0, phy_adress = 0, phy_id = 0x0 phytype doesn't match
This in turn causes USXGMII MAC autoneg bit to not get set and then UNIPHY
autoneg will time out, causing the 10G ports not to work:
[ 37.292784] uniphy autoneg time out!
So, lets detect C45 reads and writes by the magic BIT(30) in the register
argument and if so call separate C45 mdiobus read/write functions.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
include/init/ssdk_plat.h | 7 +++++++
src/init/ssdk_plat.c | 30 ++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+)
--- a/include/init/ssdk_plat.h
+++ b/include/init/ssdk_plat.h
@@ -505,3 +505,10 @@ void ssdk_plat_exit(a_uint32_t dev_id);
#endif
/*qca808x_end*/
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0))
+#define MII_ADDR_C45 (1<<30)
+#define MII_DEVADDR_C45_SHIFT 16
+#define MII_DEVADDR_C45_MASK GENMASK(20, 16)
+#define MII_REGADDR_C45_MASK GENMASK(15, 0)
+#endif
--- a/src/init/ssdk_plat.c
+++ b/src/init/ssdk_plat.c
@@ -356,6 +356,18 @@ phy_addr_validation_check(a_uint32_t phy
return A_TRUE;
}
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0))
+static inline u16 mdiobus_c45_regad(u32 regnum)
+{
+ return FIELD_GET(MII_REGADDR_C45_MASK, regnum);
+}
+
+static inline u16 mdiobus_c45_devad(u32 regnum)
+{
+ return FIELD_GET(MII_DEVADDR_C45_MASK, regnum);
+}
+#endif
+
sw_error_t
qca_ar8327_phy_read(a_uint32_t dev_id, a_uint32_t phy_addr,
a_uint32_t reg, a_uint16_t* data)
@@ -371,9 +383,18 @@ qca_ar8327_phy_read(a_uint32_t dev_id, a
if (!bus)
return SW_NOT_SUPPORTED;
phy_addr = TO_PHY_ADDR(phy_addr);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0))
+ mutex_lock(&bus->mdio_lock);
+ if (reg & MII_ADDR_C45)
+ *data = __mdiobus_c45_read(bus, phy_addr, mdiobus_c45_devad(reg), mdiobus_c45_regad(reg));
+ else
+ *data = __mdiobus_read(bus, phy_addr, reg);
+ mutex_unlock(&bus->mdio_lock);
+#else
mutex_lock(&bus->mdio_lock);
*data = __mdiobus_read(bus, phy_addr, reg);
mutex_unlock(&bus->mdio_lock);
+#endif
return 0;
}
@@ -393,9 +414,18 @@ qca_ar8327_phy_write(a_uint32_t dev_id,
if (!bus)
return SW_NOT_SUPPORTED;
phy_addr = TO_PHY_ADDR(phy_addr);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,3,0))
+ mutex_lock(&bus->mdio_lock);
+ if (reg & MII_ADDR_C45)
+ __mdiobus_c45_write(bus, phy_addr, mdiobus_c45_devad(reg), mdiobus_c45_regad(reg), data);
+ else
+ __mdiobus_write(bus, phy_addr, reg, data);
+ mutex_unlock(&bus->mdio_lock);
+#else
mutex_lock(&bus->mdio_lock);
__mdiobus_write(bus, phy_addr, reg, data);
mutex_unlock(&bus->mdio_lock);
+#endif
return 0;
}

2
package/kernel/qca-ssdk/patches/200-allow-parallel-build.patch
View File

@ -40,7 +40,7 @@
kslib_c:
--- a/make/linux_opt.mk
+++ b/make/linux_opt.mk
@@ -777,6 +777,6 @@ LOCAL_CFLAGS += $(CPU_CFLAG) -D"KBUILD_M
@@ -778,6 +778,6 @@ LOCAL_CFLAGS += $(CPU_CFLAG) -D"KBUILD_M
####################################################################
# cflags for LNX Modules-Style Makefile
####################################################################

31
package/kernel/qca-ssdk/patches/201-fix-compile-warnings.patch Normal file
View File

@ -0,0 +1,31 @@
--- a/src/fal/fal_port_ctrl.c
+++ b/src/fal/fal_port_ctrl.c
@@ -2089,7 +2089,7 @@ fal_port_hibernate_get (a_uint32_t dev_i
*/
sw_error_t
fal_port_cdt (a_uint32_t dev_id, fal_port_t port_id, a_uint32_t mdi_pair,
- a_uint32_t * cable_status, a_uint32_t * cable_len)
+ fal_cable_status_t * cable_status, a_uint32_t * cable_len)
{
sw_error_t rv;
--- a/src/fal/fal_portvlan.c
+++ b/src/fal/fal_portvlan.c
@@ -2173,7 +2173,7 @@ fal_netisolate_get(a_uint32_t dev_id, a_
* @return SW_OK or error code
*/
sw_error_t
-fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_bool_t enable)
+fal_eg_trans_filter_bypass_en_set(a_uint32_t dev_id, a_uint32_t enable)
{
sw_error_t rv;
@@ -2190,7 +2190,7 @@ fal_eg_trans_filter_bypass_en_set(a_uint
* @return SW_OK or error code
*/
sw_error_t
-fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_bool_t* enable)
+fal_eg_trans_filter_bypass_en_get(a_uint32_t dev_id, a_uint32_t* enable)
{
sw_error_t rv;