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uboot-rockchip: add dedicated uboot for LinkEase EasePi R1
The generic-rk3568 does not reset the gmac phy, causing the kernel to fail to initialize gmac during cold boot with the error message "mdio_bus stmmac-1: MDIO device at address 1 is missing." Adding a dedicated uboot for EasePi R1 to resolve this issue. The EasePi R1's DTS hasn't been merged into the Linux release yet, so it cannot be submitted to the upstream u-boot. Fixes:ef093299db("uboot-rockchip: add support for LinkEase EasePi R1") Signed-off-by: Liangbin Lian <jjm2473@gmail.com> Link: https://github.com/openwrt/openwrt/pull/20772 (cherry picked from commit5dff7b45d3) With changes: 1. Reorder patch file names (`105-*` to `106-*`). 2. configs/easepi-r1-rk3568_defconfig needs CONFIG_SPL_PAD_TO on u-boot 2024.10. Signed-off-by: Liangbin Lian <jjm2473@gmail.com> Link: https://github.com/openwrt/openwrt/pull/20744 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Liangbin Lian
Hauke Mehrtens
parent
fbaf5271d2
commit
9c25d39d3e
@ -219,6 +219,13 @@ define U-Boot/bpi-r2-pro-rk3568
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sinovoip_bpi-r2-pro
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endef
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define U-Boot/easepi-r1-rk3568
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$(U-Boot/rk3568/Default)
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NAME:=LinkEase EasePi R1
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BUILD_DEVICES:= \
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linkease_easepi-r1
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endef
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define U-Boot/fastrhino-r66s-rk3568
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$(U-Boot/rk3568/Default)
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NAME:=FastRhino R66S
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@ -226,13 +233,6 @@ define U-Boot/fastrhino-r66s-rk3568
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lunzn_fastrhino-r66s
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endef
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define U-Boot/generic-rk3568
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$(U-Boot/rk3568/Default)
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NAME:=Generic RK3566/RK3568 board
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BUILD_DEVICES:= \
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linkease_easepi-r1
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endef
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define U-Boot/nanopi-r5c-rk3568
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$(U-Boot/rk3568/Default)
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NAME:=NanoPi R5C
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@ -347,8 +347,8 @@ UBOOT_TARGETS := \
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radxa-zero-3-rk3566 \
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rock-3c-rk3566 \
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bpi-r2-pro-rk3568 \
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easepi-r1-rk3568 \
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fastrhino-r66s-rk3568 \
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generic-rk3568 \
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nanopi-r5c-rk3568 \
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nanopi-r5s-rk3568 \
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radxa-e25-rk3568 \
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@ -0,0 +1,662 @@
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From 63d60b21fd4933080ff22bdc21652f7c2a14bc52 Mon Sep 17 00:00:00 2001
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From: Liangbin Lian <jjm2473@gmail.com>
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Date: Tue, 14 Oct 2025 13:12:26 +0800
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Subject: [PATCH 1/2] arm64: dts: rockchip: add LinkEase EasePi R1
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LinkEase EasePi R1 [1] is a high-performance mini router.
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Specification:
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- Rockchip RK3568
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- 2GB/4GB LPDDR4 RAM
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- 16GB on-board eMMC
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- 1x M.2 key for 2280 NVMe (PCIe 3.0)
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- 1x USB 3.0 Type-A
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- 1x USB 2.0 Type-C (for USB flashing)
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- 2x 1000 Base-T (native, RTL8211F)
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- 2x 2500 Base-T (PCIe, RTL8125B)
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- 1x HDMI 2.0 Output
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- 12v DC Jack
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- 1x Power key connected to PMIC
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- 2x LEDs (one static power supplied, one GPIO controlled)
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[1] https://doc.linkease.com/zh/guide/easepi-r1/hardware.html
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: Liangbin Lian <jjm2473@gmail.com>
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Link: https://patch.msgid.link/20251014051226.64255-4-jjm2473@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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[ upstream commit: deaefeaf3df433d50935b9a85076041040f06d74 ]
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Signed-off-by: Liangbin Lian <jjm2473@gmail.com>
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---
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.../src/arm64/rockchip/rk3568-easepi-r1.dts | 623 ++++++++++++++++++
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1 file changed, 623 insertions(+)
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create mode 100644 dts/upstream/src/arm64/rockchip/rk3568-easepi-r1.dts
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--- /dev/null
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+++ b/dts/upstream/src/arm64/rockchip/rk3568-easepi-r1.dts
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@@ -0,0 +1,623 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/input/input.h>
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+#include <dt-bindings/leds/common.h>
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+#include <dt-bindings/pinctrl/rockchip.h>
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+#include <dt-bindings/soc/rockchip,vop2.h>
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+#include "rk3568.dtsi"
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+
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+/ {
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+ model = "LinkEase EasePi R1";
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+ compatible = "linkease,easepi-r1", "rockchip,rk3568";
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+
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+ aliases {
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+ ethernet0 = &gmac0;
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+ ethernet1 = &gmac1;
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+ mmc0 = &sdhci;
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+ };
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+
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+ chosen: chosen {
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+ stdout-path = "serial2:1500000n8";
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+ };
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+
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+ adc-keys {
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+ compatible = "adc-keys";
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+ io-channels = <&saradc 0>;
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+ io-channel-names = "buttons";
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+ keyup-threshold-microvolt = <1800000>;
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+
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+ button-recovery {
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+ label = "Recovery";
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+ linux,code = <KEY_VENDOR>;
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+ press-threshold-microvolt = <1750>;
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+ };
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+ };
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+
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+ gpio-leds {
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+ compatible = "gpio-leds";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&status_led_pin>;
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+
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+ status_led: led-status {
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+ color = <LED_COLOR_ID_GREEN>;
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+ function = LED_FUNCTION_STATUS;
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+ gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>;
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+ linux,default-trigger = "heartbeat";
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+ };
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+ };
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+
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+ hdmi-con {
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+ compatible = "hdmi-connector";
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+ type = "a";
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+
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+ port {
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+ hdmi_con_in: endpoint {
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+ remote-endpoint = <&hdmi_out_con>;
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+ };
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+ };
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+ };
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+
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+ dc_12v: regulator-dc-12v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "dc_12v";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <12000000>;
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+ regulator-max-microvolt = <12000000>;
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+ };
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+
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+ vcc5v0_sys: regulator-vcc5v0-sys {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc5v0_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ vin-supply = <&dc_12v>;
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+ };
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+
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+ vcc3v3_sys: regulator-vcc3v3-sys {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc3v3_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ vin-supply = <&dc_12v>;
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+ };
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+
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+ pcie30_avdd0v9: regulator-pcie30-avdd0v9 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "pcie30_avdd0v9";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <900000>;
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+ regulator-max-microvolt = <900000>;
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+ vin-supply = <&vcc3v3_sys>;
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+ };
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+
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+ pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "pcie30_avdd1v8";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ vin-supply = <&vcc3v3_sys>;
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+ };
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+
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+ regulator-vdd0v95-25glan {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vdd0v95_25glan_en>;
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+ regulator-name = "vdd0v95_25glan";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <950000>;
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+ regulator-max-microvolt = <950000>;
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+ vin-supply = <&vcc3v3_sys>;
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+ };
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+
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+ vcc3v3_nvme: regulator-vcc3v3-nvme {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&vcc3v3_nvme_en>;
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+ regulator-name = "vcc3v3_nvme";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ vin-supply = <&dc_12v>;
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+ };
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+
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+};
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+
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+&combphy1 {
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+ status = "okay";
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+};
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+
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+&combphy2 {
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+ status = "okay";
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+};
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+
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+&cpu0 {
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+ cpu-supply = <&vdd_cpu>;
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+};
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+
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+&cpu1 {
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+ cpu-supply = <&vdd_cpu>;
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+};
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+
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+&cpu2 {
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+ cpu-supply = <&vdd_cpu>;
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+};
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+
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+&cpu3 {
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+ cpu-supply = <&vdd_cpu>;
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+};
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+
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+&gmac0 {
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+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
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+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
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+ assigned-clock-rates = <0>, <125000000>;
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+ phy-handle = <&rgmii_phy0>;
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+ phy-mode = "rgmii-id";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gmac0_miim
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+ &gmac0_tx_bus2
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+ &gmac0_rx_bus2
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+ &gmac0_rgmii_clk
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+ &gmac0_rgmii_bus>;
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+ status = "okay";
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+};
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+
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+&gmac1 {
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+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
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+ assigned-clock-rates = <0>, <125000000>;
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+ phy-handle = <&rgmii_phy1>;
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+ phy-mode = "rgmii-id";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gmac1m1_miim
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+ &gmac1m1_tx_bus2
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+ &gmac1m1_rx_bus2
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+ &gmac1m1_rgmii_clk
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+ &gmac1m1_rgmii_bus>;
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+ status = "okay";
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+};
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+
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+&gpu {
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+ mali-supply = <&vdd_gpu>;
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+ status = "okay";
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+};
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+
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+&hdmi {
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+ avdd-0v9-supply = <&vdda0v9_image>;
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+ avdd-1v8-supply = <&vcca1v8_image>;
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+ status = "okay";
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+};
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+
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+&hdmi_in {
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+ hdmi_in_vp0: endpoint {
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+ remote-endpoint = <&vp0_out_hdmi>;
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+ };
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+};
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+
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+&hdmi_out {
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+ hdmi_out_con: endpoint {
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+ remote-endpoint = <&hdmi_con_in>;
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+ };
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+};
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+
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+&hdmi_sound {
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+
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+ vdd_cpu: regulator@1c {
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+ compatible = "tcs,tcs4525";
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+ reg = <0x1c>;
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+ fcs,suspend-voltage-selector = <1>;
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+ regulator-name = "vdd_cpu";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <800000>;
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+ regulator-max-microvolt = <1150000>;
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+ regulator-ramp-delay = <2300>;
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+ vin-supply = <&vcc5v0_sys>;
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+
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+
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+ rk809: pmic@20 {
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+ compatible = "rockchip,rk809";
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+ reg = <0x20>;
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+ interrupt-parent = <&gpio0>;
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+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
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+ #clock-cells = <1>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pmic_int>;
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+ system-power-controller;
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+ vcc1-supply = <&vcc3v3_sys>;
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+ vcc2-supply = <&vcc3v3_sys>;
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+ vcc3-supply = <&vcc3v3_sys>;
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+ vcc4-supply = <&vcc3v3_sys>;
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+ vcc5-supply = <&vcc3v3_sys>;
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+ vcc6-supply = <&vcc3v3_sys>;
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+ vcc7-supply = <&vcc3v3_sys>;
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+ vcc8-supply = <&vcc3v3_sys>;
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+ vcc9-supply = <&vcc3v3_sys>;
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+ wakeup-source;
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+
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+ regulators {
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+ vdd_logic: DCDC_REG1 {
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+ regulator-name = "vdd_logic";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-initial-mode = <0x2>;
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+ regulator-min-microvolt = <500000>;
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+ regulator-max-microvolt = <1350000>;
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+ regulator-ramp-delay = <6001>;
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+
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+
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+ vdd_gpu: DCDC_REG2 {
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+ regulator-name = "vdd_gpu";
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+ regulator-always-on;
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+ regulator-initial-mode = <0x2>;
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+ regulator-min-microvolt = <500000>;
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+ regulator-max-microvolt = <1350000>;
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+ regulator-ramp-delay = <6001>;
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+
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+
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+ vcc_ddr: DCDC_REG3 {
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+ regulator-name = "vcc_ddr";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-initial-mode = <0x2>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+
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+ vdd_npu: DCDC_REG4 {
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+ regulator-name = "vdd_npu";
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+ regulator-initial-mode = <0x2>;
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+ regulator-min-microvolt = <500000>;
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+ regulator-max-microvolt = <1350000>;
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+ regulator-ramp-delay = <6001>;
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+
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
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+ };
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+
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+ vcc_1v8: DCDC_REG5 {
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+ regulator-name = "vcc_1v8";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
|
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+ regulator-max-microvolt = <1800000>;
|
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+
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+ regulator-state-mem {
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+ regulator-off-in-suspend;
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+ };
|
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+ };
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+
|
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+ vdda0v9_image: LDO_REG1 {
|
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+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-min-microvolt = <950000>;
|
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+ regulator-max-microvolt = <950000>;
|
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+
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+ regulator-state-mem {
|
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+ regulator-off-in-suspend;
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+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
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+ regulator-name = "vdda_0v9";
|
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+ regulator-always-on;
|
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+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
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+ regulator-state-mem {
|
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+ regulator-off-in-suspend;
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+ };
|
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+ };
|
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+
|
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+ vdda0v9_pmu: LDO_REG3 {
|
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+ regulator-name = "vdda0v9_pmu";
|
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+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2s0_8ch {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mdio0 {
|
||||
+ rgmii_phy0: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0x1>;
|
||||
+ pinctrl-0 = <ð_phy0_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <20000>;
|
||||
+ reset-deassert-us = <100000>;
|
||||
+ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&mdio1 {
|
||||
+ rgmii_phy1: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0x1>;
|
||||
+ pinctrl-0 = <ð_phy1_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <20000>;
|
||||
+ reset-deassert-us = <100000>;
|
||||
+ reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+/* ETH3 */
|
||||
+&pcie2x1 {
|
||||
+ reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie30phy {
|
||||
+ data-lanes = <1 2>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* ETH2 */
|
||||
+&pcie3x1 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* M.2 Key for 2280 NVMe */
|
||||
+&pcie3x2 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_nvme>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gmac0 {
|
||||
+ eth_phy0_reset_pin: eth-phy0-reset-pin {
|
||||
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gmac1 {
|
||||
+ eth_phy1_reset_pin: eth-phy1-reset-pin {
|
||||
+ rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ status_led_pin: status-led-pin {
|
||||
+ rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ nvme {
|
||||
+ vcc3v3_nvme_en: vcc3v3-nvme-en {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie-nic {
|
||||
+ vdd0v95_25glan_en: vdd0v95-25glan-en {
|
||||
+ rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int: pmic-int {
|
||||
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmuio1-supply = <&vcc3v3_pmu>;
|
||||
+ pmuio2-supply = <&vcc3v3_pmu>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcc_1v8>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_1v8>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <200000000>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+/* OTG Only USB2.0, Only device mode */
|
||||
+&usb_host0_xhci {
|
||||
+ dr_mode = "peripheral";
|
||||
+ extcon = <&usb2phy0>;
|
||||
+ maximum-speed = "high-speed";
|
||||
+ phys = <&usb2phy0_otg>;
|
||||
+ phy-names = "usb2-phy";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_sys>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop {
|
||||
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vp0 {
|
||||
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
+ remote-endpoint = <&hdmi_in_vp0>;
|
||||
+ };
|
||||
+};
|
||||
@ -0,0 +1,124 @@
|
||||
From bb1996b423b81b94b1468fffe5eb9949434b941e Mon Sep 17 00:00:00 2001
|
||||
From: Liangbin Lian <jjm2473@gmail.com>
|
||||
Date: Thu, 13 Nov 2025 14:51:21 +0800
|
||||
Subject: [PATCH 2/2] board: rockchip: add LinkEase EasePi R1
|
||||
|
||||
LinkEase EasePi R1 [1] is a high-performance mini router.
|
||||
|
||||
Specification:
|
||||
- Rockchip RK3568
|
||||
- 2GB/4GB LPDDR4 RAM
|
||||
- 16GB on-board eMMC
|
||||
- 1x M.2 key for 2280 NVMe (PCIe 3.0)
|
||||
- 1x USB 3.0 Type-A
|
||||
- 1x USB 2.0 Type-C (for USB flashing)
|
||||
- 2x 1000 Base-T (native, RTL8211F)
|
||||
- 2x 2500 Base-T (PCIe, RTL8125B)
|
||||
- 1x HDMI 2.0 Output
|
||||
- 12v DC Jack
|
||||
- 1x Power key connected to PMIC
|
||||
- 2x LEDs (one static power supplied, one GPIO controlled)
|
||||
|
||||
[1] https://doc.linkease.com/zh/guide/easepi-r1/hardware.html
|
||||
|
||||
Signed-off-by: Liangbin Lian <jjm2473@gmail.com>
|
||||
---
|
||||
arch/arm/dts/rk3568-easepi-r1-u-boot.dtsi | 3 +
|
||||
configs/easepi-r1-rk3568_defconfig | 84 +++++++++++++++++++++++
|
||||
2 files changed, 87 insertions(+)
|
||||
create mode 100644 arch/arm/dts/rk3568-easepi-r1-u-boot.dtsi
|
||||
create mode 100644 configs/easepi-r1-rk3568_defconfig
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/dts/rk3568-easepi-r1-u-boot.dtsi
|
||||
@@ -0,0 +1,3 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+
|
||||
+#include "rk356x-u-boot.dtsi"
|
||||
--- /dev/null
|
||||
+++ b/configs/easepi-r1-rk3568_defconfig
|
||||
@@ -0,0 +1,84 @@
|
||||
+CONFIG_ARM=y
|
||||
+CONFIG_SKIP_LOWLEVEL_INIT=y
|
||||
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
|
||||
+CONFIG_COUNTER_FREQUENCY=24000000
|
||||
+CONFIG_ARCH_ROCKCHIP=y
|
||||
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-easepi-r1"
|
||||
+CONFIG_ROCKCHIP_RK3568=y
|
||||
+CONFIG_SPL_SERIAL=y
|
||||
+CONFIG_SYS_LOAD_ADDR=0xc00800
|
||||
+CONFIG_DEBUG_UART_BASE=0xFE660000
|
||||
+CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
+CONFIG_PCI=y
|
||||
+CONFIG_DEBUG_UART=y
|
||||
+CONFIG_FIT=y
|
||||
+CONFIG_FIT_VERBOSE=y
|
||||
+CONFIG_SPL_FIT_SIGNATURE=y
|
||||
+CONFIG_SPL_LOAD_FIT=y
|
||||
+CONFIG_LEGACY_IMAGE_FORMAT=y
|
||||
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-easepi-r1.dtb"
|
||||
+# CONFIG_DISPLAY_CPUINFO is not set
|
||||
+CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
+CONFIG_SPL_MAX_SIZE=0x40000
|
||||
+CONFIG_SPL_PAD_TO=0x7f8000
|
||||
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
|
||||
+CONFIG_SPL_ATF=y
|
||||
+CONFIG_CMD_GPIO=y
|
||||
+CONFIG_CMD_GPT=y
|
||||
+CONFIG_CMD_I2C=y
|
||||
+CONFIG_CMD_MMC=y
|
||||
+CONFIG_CMD_PCI=y
|
||||
+CONFIG_CMD_USB=y
|
||||
+CONFIG_CMD_ROCKUSB=y
|
||||
+CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
+CONFIG_CMD_PMIC=y
|
||||
+CONFIG_CMD_REGULATOR=y
|
||||
+# CONFIG_SPL_DOS_PARTITION is not set
|
||||
+CONFIG_SPL_OF_CONTROL=y
|
||||
+CONFIG_OF_LIVE=y
|
||||
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
|
||||
+CONFIG_SPL_DM_SEQ_ALIAS=y
|
||||
+CONFIG_SPL_REGMAP=y
|
||||
+CONFIG_SPL_SYSCON=y
|
||||
+CONFIG_SPL_CLK=y
|
||||
+# CONFIG_USB_FUNCTION_FASTBOOT is not set
|
||||
+CONFIG_ROCKCHIP_GPIO=y
|
||||
+CONFIG_SYS_I2C_ROCKCHIP=y
|
||||
+CONFIG_MISC=y
|
||||
+CONFIG_SUPPORT_EMMC_RPMB=y
|
||||
+CONFIG_MMC_DW=y
|
||||
+CONFIG_MMC_DW_ROCKCHIP=y
|
||||
+CONFIG_MMC_SDHCI=y
|
||||
+CONFIG_MMC_SDHCI_SDMA=y
|
||||
+CONFIG_MMC_SDHCI_ROCKCHIP=y
|
||||
+CONFIG_PHY_REALTEK=y
|
||||
+CONFIG_DWC_ETH_QOS=y
|
||||
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
|
||||
+CONFIG_RTL8169=y
|
||||
+CONFIG_NVME_PCI=y
|
||||
+CONFIG_PCIE_DW_ROCKCHIP=y
|
||||
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
|
||||
+CONFIG_SPL_PINCTRL=y
|
||||
+CONFIG_DM_PMIC=y
|
||||
+CONFIG_PMIC_RK8XX=y
|
||||
+CONFIG_REGULATOR_RK8XX=y
|
||||
+CONFIG_PWM_ROCKCHIP=y
|
||||
+CONFIG_SPL_RAM=y
|
||||
+CONFIG_BAUDRATE=1500000
|
||||
+CONFIG_DEBUG_UART_SHIFT=2
|
||||
+CONFIG_SYS_NS16550_MEM32=y
|
||||
+CONFIG_SYSRESET=y
|
||||
+CONFIG_USB=y
|
||||
+CONFIG_USB_XHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_HCD=y
|
||||
+CONFIG_USB_EHCI_GENERIC=y
|
||||
+CONFIG_USB_OHCI_HCD=y
|
||||
+CONFIG_USB_OHCI_GENERIC=y
|
||||
+CONFIG_USB_DWC3=y
|
||||
+CONFIG_USB_DWC3_GENERIC=y
|
||||
+CONFIG_SPL_USB_DWC3_GENERIC=y
|
||||
+CONFIG_USB_GADGET=y
|
||||
+CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
+CONFIG_USB_FUNCTION_ROCKUSB=y
|
||||
+CONFIG_ERRNO_STR=y
|
||||
Loading…
Reference in New Issue
Block a user