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add 2.6.32 support

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SVN-Revision: 19519
This commit is contained in:
Florian Fainelli 2010-02-04 14:35:26 +00:00
parent dad3df8582
commit 917d883e0c
7 changed files with 1222 additions and 0 deletions
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141
target/linux/ar7/config-2.6.32 Normal file
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@ -0,0 +1,141 @@
CONFIG_32BIT=y
# CONFIG_64BIT is not set
# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
CONFIG_AR7=y
CONFIG_AR7_GPIO=y
CONFIG_AR7_WDT=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
# CONFIG_ARCH_SUPPORTS_MSI is not set
CONFIG_ARCH_SUPPORTS_OPROFILE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# CONFIG_BCM47XX is not set
# CONFIG_BCM63XX is not set
CONFIG_BITREVERSE=y
CONFIG_BOOT_ELF32=y
# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
CONFIG_CEVT_R4K=y
CONFIG_CEVT_R4K_LIB=y
CONFIG_CFG80211_DEFAULT_PS_VALUE=0
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
CONFIG_CPMAC=y
# CONFIG_CPU_BIG_ENDIAN is not set
# CONFIG_CPU_CAVIUM_OCTEON is not set
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_CPU_LITTLE_ENDIAN=y
# CONFIG_CPU_LOONGSON2E is not set
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
CONFIG_CPU_MIPSR1=y
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R5500 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_VR41XX is not set
CONFIG_CSRC_R4K=y
CONFIG_CSRC_R4K_LIB=y
CONFIG_DECOMPRESS_LZMA=y
# CONFIG_DM9000 is not set
CONFIG_DMA_NEED_PCI_MAP_STATE=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_EARLY_PRINTK=y
CONFIG_FIXED_PHY=y
# CONFIG_FSNOTIFY is not set
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HW_RANDOM=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQ_CPU=y
# CONFIG_ISDN is not set
CONFIG_KALLSYMS=y
CONFIG_LEDS_GPIO=y
# CONFIG_MACH_ALCHEMY is not set
# CONFIG_MACH_DECSTATION is not set
# CONFIG_MACH_JAZZ is not set
# CONFIG_MACH_LOONGSON is not set
# CONFIG_MACH_TX39XX is not set
# CONFIG_MACH_TX49XX is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_MIKROTIK_RB532 is not set
CONFIG_MIPS=y
# CONFIG_MIPS_COBALT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_MACHINE is not set
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_MT_DISABLED=y
# CONFIG_MIPS_MT_SMP is not set
# CONFIG_MIPS_MT_SMTC is not set
# CONFIG_MIPS_SIM is not set
CONFIG_MTD_AR7_PARTS=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_PHYSMAP=y
CONFIG_NO_EXCEPT_FILL=y
# CONFIG_NO_IOPORT is not set
# CONFIG_NXP_STB220 is not set
# CONFIG_NXP_STB225 is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PHYLIB=y
# CONFIG_PMC_MSP is not set
# CONFIG_PMC_YOSEMITE is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_PNX8550_STB810 is not set
# CONFIG_PROBE_INITRD_HEADER is not set
CONFIG_SCHED_OMIT_FRAME_POINTER=y
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250_EXTENDED is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP28 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_BIGSUR is not set
# CONFIG_SIBYTE_CARMEL is not set
# CONFIG_SIBYTE_CRHINE is not set
# CONFIG_SIBYTE_CRHONE is not set
# CONFIG_SIBYTE_LITTLESUR is not set
# CONFIG_SIBYTE_RHONE is not set
# CONFIG_SIBYTE_SENTOSA is not set
# CONFIG_SIBYTE_SWARM is not set
CONFIG_SWAP_IO_SPACE=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
CONFIG_TRAD_SIGNALS=y
# CONFIG_TREE_PREEMPT_RCU is not set
CONFIG_TREE_RCU=y
CONFIG_VLYNQ=y
CONFIG_ZONE_DMA_FLAG=0

158
target/linux/ar7/files-2.6.32/drivers/char/ar7_gpio.c Normal file
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@ -0,0 +1,158 @@
/*
* Copyright (C) 2007 Nicolas Thill <nico@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/device.h>
#include <linux/fs.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include <linux/types.h>
#include <linux/cdev.h>
#include <gpio.h>
#define DRVNAME "ar7_gpio"
#define LONGNAME "TI AR7 GPIOs Driver"
MODULE_AUTHOR("Nicolas Thill <nico@openwrt.org>");
MODULE_DESCRIPTION(LONGNAME);
MODULE_LICENSE("GPL");
static int ar7_gpio_major;
static ssize_t ar7_gpio_write(struct file *file, const char __user *buf,
size_t len, loff_t *ppos)
{
int pin = iminor(file->f_dentry->d_inode);
size_t i;
for (i = 0; i < len; ++i) {
char c;
if (get_user(c, buf + i))
return -EFAULT;
switch (c) {
case '0':
gpio_set_value(pin, 0);
break;
case '1':
gpio_set_value(pin, 1);
break;
case 'd':
case 'D':
ar7_gpio_disable(pin);
break;
case 'e':
case 'E':
ar7_gpio_enable(pin);
break;
case 'i':
case 'I':
case '<':
gpio_direction_input(pin);
break;
case 'o':
case 'O':
case '>':
gpio_direction_output(pin, 0);
break;
default:
return -EINVAL;
}
}
return len;
}
static ssize_t ar7_gpio_read(struct file *file, char __user *buf,
size_t len, loff_t *ppos)
{
int pin = iminor(file->f_dentry->d_inode);
int value;
value = gpio_get_value(pin);
if (put_user(value ? '1' : '0', buf))
return -EFAULT;
return 1;
}
static int ar7_gpio_open(struct inode *inode, struct file *file)
{
int m = iminor(inode);
if (m >= (ar7_is_titan() ? TITAN_GPIO_MAX : AR7_GPIO_MAX))
return -EINVAL;
return nonseekable_open(inode, file);
}
static int ar7_gpio_release(struct inode *inode, struct file *file)
{
return 0;
}
static const struct file_operations ar7_gpio_fops = {
.owner = THIS_MODULE,
.write = ar7_gpio_write,
.read = ar7_gpio_read,
.open = ar7_gpio_open,
.release = ar7_gpio_release,
.llseek = no_llseek,
};
static struct platform_device *ar7_gpio_device;
static int __init ar7_gpio_init(void)
{
int rc;
ar7_gpio_device = platform_device_alloc(DRVNAME, -1);
if (!ar7_gpio_device)
return -ENOMEM;
rc = platform_device_add(ar7_gpio_device);
if (rc < 0)
goto out_put;
rc = register_chrdev(ar7_gpio_major, DRVNAME, &ar7_gpio_fops);
if (rc < 0)
goto out_put;
ar7_gpio_major = rc;
rc = 0;
goto out;
out_put:
platform_device_put(ar7_gpio_device);
out:
return rc;
}
static void __exit ar7_gpio_exit(void)
{
unregister_chrdev(ar7_gpio_major, DRVNAME);
platform_device_unregister(ar7_gpio_device);
}
module_init(ar7_gpio_init);
module_exit(ar7_gpio_exit);

11
target/linux/ar7/patches-2.6.32/110-flash.patch Normal file
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@ -0,0 +1,11 @@
--- a/drivers/mtd/maps/physmap.c
+++ b/drivers/mtd/maps/physmap.c
@@ -80,7 +80,7 @@ static const char *rom_probe_types[] = {
"map_rom",
NULL };
#ifdef CONFIG_MTD_PARTITIONS
-static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL };
+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "ar7part", NULL };
#endif
static int physmap_flash_probe(struct platform_device *dev)

28
target/linux/ar7/patches-2.6.32/120-gpio_chrdev.patch Normal file
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@ -0,0 +1,28 @@
--- a/drivers/char/Kconfig
+++ b/drivers/char/Kconfig
@@ -987,6 +987,15 @@ config MWAVE
To compile this driver as a module, choose M here: the
module will be called mwave.
+config AR7_GPIO
+ tristate "TI AR7 GPIO Support"
+ depends on AR7
+ help
+ Give userspace access to the GPIO pins on the Texas Instruments AR7
+ processors.
+
+ If compiled as a module, it will be called ar7_gpio.
+
config SCx200_GPIO
tristate "NatSemi SCx200 GPIO Support"
depends on SCx200
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -92,6 +92,7 @@ obj-$(CONFIG_HW_RANDOM) += hw_random/
obj-$(CONFIG_PPDEV) += ppdev.o
obj-$(CONFIG_NWBUTTON) += nwbutton.o
obj-$(CONFIG_NWFLASH) += nwflash.o
+obj-$(CONFIG_AR7_GPIO) += ar7_gpio.o
obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o
obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o
obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o

28
target/linux/ar7/patches-2.6.32/500-serial_kludge.patch Normal file
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@ -0,0 +1,28 @@
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -296,6 +296,13 @@ static const struct serial8250_config ua
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
+ [PORT_AR7] = {
+ .name = "TI-AR7",
+ .fifo_size = 16,
+ .tx_loadsz = 16,
+ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
+ .flags = UART_CAP_FIFO | UART_CAP_AFE,
+ },
};
#if defined (CONFIG_SERIAL_8250_AU1X00)
@@ -2712,7 +2719,11 @@ static void serial8250_console_putchar(s
{
struct uart_8250_port *up = (struct uart_8250_port *)port;
+#ifdef CONFIG_AR7
+ wait_for_xmitr(up, BOTH_EMPTY);
+#else
wait_for_xmitr(up, UART_LSR_THRE);
+#endif
serial_out(up, UART_TX, ch);
}

784
target/linux/ar7/patches-2.6.32/930-titan-platform.patch Normal file
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@ -0,0 +1,784 @@
Index: linux-2.6.32.7/arch/mips/ar7/platform.c
===================================================================
--- linux-2.6.32.7.orig/arch/mips/ar7/platform.c 2010-01-29 00:06:20.000000000 +0100
+++ linux-2.6.32.7/arch/mips/ar7/platform.c 2010-02-04 14:40:23.000000000 +0100
@@ -131,6 +131,36 @@
},
};
+static struct resource cpmac_low_res_titan[] = {
+ {
+ .name = "regs",
+ .flags = IORESOURCE_MEM,
+ .start = TITAN_REGS_MAC0,
+ .end = TITAN_REGS_MAC0 + 0x7ff,
+ },
+ {
+ .name = "irq",
+ .flags = IORESOURCE_IRQ,
+ .start = 27,
+ .end = 27,
+ },
+};
+
+static struct resource cpmac_high_res_titan[] = {
+ {
+ .name = "regs",
+ .flags = IORESOURCE_MEM,
+ .start = TITAN_REGS_MAC1,
+ .end = TITAN_REGS_MAC1 + 0x7ff,
+ },
+ {
+ .name = "irq",
+ .flags = IORESOURCE_IRQ,
+ .start = 41,
+ .end = 41,
+ },
+};
+
static struct resource vlynq_low_res[] = {
{
.name = "regs",
@@ -185,6 +215,60 @@
},
};
+static struct resource vlynq_low_res_titan[] = {
+ {
+ .name = "regs",
+ .flags = IORESOURCE_MEM,
+ .start = TITAN_REGS_VLYNQ0,
+ .end = TITAN_REGS_VLYNQ0 + 0xff,
+ },
+ {
+ .name = "irq",
+ .flags = IORESOURCE_IRQ,
+ .start = 33,
+ .end = 33,
+ },
+ {
+ .name = "mem",
+ .flags = IORESOURCE_MEM,
+ .start = 0x0c000000,
+ .end = 0x0fffffff,
+ },
+ {
+ .name = "devirq",
+ .flags = IORESOURCE_IRQ,
+ .start = 80,
+ .end = 111,
+ },
+};
+
+static struct resource vlynq_high_res_titan[] = {
+ {
+ .name = "regs",
+ .flags = IORESOURCE_MEM,
+ .start = TITAN_REGS_VLYNQ1,
+ .end = TITAN_REGS_VLYNQ1 + 0xff,
+ },
+ {
+ .name = "irq",
+ .flags = IORESOURCE_IRQ,
+ .start = 34,
+ .end = 34,
+ },
+ {
+ .name = "mem",
+ .flags = IORESOURCE_MEM,
+ .start = 0x40000000,
+ .end = 0x43ffffff,
+ },
+ {
+ .name = "devirq",
+ .flags = IORESOURCE_IRQ,
+ .start = 112,
+ .end = 143,
+ },
+};
+
static struct resource usb_res[] = {
{
.name = "regs",
@@ -228,6 +312,18 @@
.phy_mask = 0x7fffffff,
};
+static struct plat_cpmac_data cpmac_low_data_titan = {
+ .reset_bit = 17,
+ .power_bit = 20,
+ .phy_mask = 0x40000000,
+};
+
+static struct plat_cpmac_data cpmac_high_data_titan = {
+ .reset_bit = 21,
+ .power_bit = 22,
+ .phy_mask = 0x80000000,
+};
+
static struct plat_vlynq_data vlynq_low_data = {
.ops.on = vlynq_on,
.ops.off = vlynq_off,
@@ -242,6 +338,20 @@
.gpio_bit = 19,
};
+static struct plat_vlynq_data vlynq_low_data_titan = {
+ .ops.on = vlynq_on,
+ .ops.off = vlynq_off,
+ .reset_bit = 15,
+ .gpio_bit = 14,
+};
+
+static struct plat_vlynq_data vlynq_high_data_titan = {
+ .ops.on = vlynq_on,
+ .ops.off = vlynq_off,
+ .reset_bit = 16,
+ .gpio_bit = 7,
+};
+
static struct platform_device physmap_flash = {
.id = 0,
.name = "physmap-flash",
@@ -275,6 +385,30 @@
.num_resources = ARRAY_SIZE(cpmac_high_res),
};
+static struct platform_device cpmac_low_titan = {
+ .id = 0,
+ .name = "cpmac",
+ .dev = {
+ .dma_mask = &cpmac_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &cpmac_low_data_titan,
+ },
+ .resource = cpmac_low_res_titan,
+ .num_resources = ARRAY_SIZE(cpmac_low_res_titan),
+};
+
+static struct platform_device cpmac_high_titan = {
+ .id = 1,
+ .name = "cpmac",
+ .dev = {
+ .dma_mask = &cpmac_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &cpmac_high_data_titan,
+ },
+ .resource = cpmac_high_res_titan,
+ .num_resources = ARRAY_SIZE(cpmac_high_res_titan),
+};
+
static struct platform_device vlynq_low = {
.id = 0,
.name = "vlynq",
@@ -291,6 +425,22 @@
.num_resources = ARRAY_SIZE(vlynq_high_res),
};
+static struct platform_device vlynq_low_titan = {
+ .id = 0,
+ .name = "vlynq",
+ .dev.platform_data = &vlynq_low_data_titan,
+ .resource = vlynq_low_res_titan,
+ .num_resources = ARRAY_SIZE(vlynq_low_res_titan),
+};
+
+static struct platform_device vlynq_high_titan = {
+ .id = 1,
+ .name = "vlynq",
+ .dev.platform_data = &vlynq_high_data_titan,
+ .resource = vlynq_high_res_titan,
+ .num_resources = ARRAY_SIZE(vlynq_high_res_titan),
+};
+
static struct gpio_led default_leds[] = {
{
@@ -300,6 +450,11 @@
},
};
+static struct gpio_led titan_leds[] = {
+ { .name = "status", .gpio = 8, .active_low = 1, },
+ { .name = "wifi", .gpio = 13, .active_low = 1, },
+};
+
static struct gpio_led dsl502t_leds[] = {
{
.name = "status",
@@ -496,6 +651,9 @@
} else if (strstr(prid, "DG834")) {
ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
ar7_led_data.leds = dg834g_leds;
+ } else if (strstr(prid, "CYWM")) {
+ ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
+ ar7_led_data.leds = titan_leds;
}
}
@@ -541,14 +699,18 @@
if (res)
return res;
- ar7_device_disable(vlynq_low_data.reset_bit);
- res = platform_device_register(&vlynq_low);
+ ar7_device_disable(ar7_is_titan() ? vlynq_low_data_titan.reset_bit :
+ vlynq_low_data.reset_bit);
+ res = platform_device_register(ar7_is_titan() ? &vlynq_low_titan :
+ &vlynq_low);
if (res)
return res;
if (ar7_has_high_vlynq()) {
- ar7_device_disable(vlynq_high_data.reset_bit);
- res = platform_device_register(&vlynq_high);
+ ar7_device_disable(ar7_is_titan() ? vlynq_high_data_titan.reset_bit :
+ vlynq_high_data.reset_bit);
+ res = platform_device_register(ar7_is_titan() ? &vlynq_high_titan :
+ &vlynq_high);
if (res)
return res;
}
Index: linux-2.6.32.7/arch/mips/ar7/gpio.c
===================================================================
--- linux-2.6.32.7.orig/arch/mips/ar7/gpio.c 2010-01-29 00:06:20.000000000 +0100
+++ linux-2.6.32.7/arch/mips/ar7/gpio.c 2010-02-04 14:33:24.000000000 +0100
@@ -21,11 +21,11 @@
#include <asm/mach-ar7/gpio.h>
-static const char *ar7_gpio_list[AR7_GPIO_MAX];
+static const char *ar7_gpio_list[TITAN_GPIO_MAX];
int gpio_request(unsigned gpio, const char *label)
{
- if (gpio >= AR7_GPIO_MAX)
+ if (gpio >= (ar7_is_titan() ? TITAN_GPIO_MAX : AR7_GPIO_MAX))
return -EINVAL;
if (ar7_gpio_list[gpio])
Index: linux-2.6.32.7/arch/mips/ar7/setup.c
===================================================================
--- linux-2.6.32.7.orig/arch/mips/ar7/setup.c 2010-01-29 00:06:20.000000000 +0100
+++ linux-2.6.32.7/arch/mips/ar7/setup.c 2010-02-04 14:33:24.000000000 +0100
@@ -23,6 +23,9 @@
#include <asm/reboot.h>
#include <asm/mach-ar7/ar7.h>
#include <asm/mach-ar7/prom.h>
+#include <asm/mach-ar7/gpio.h>
+
+static int titan_variant;
static void ar7_machine_restart(char *command)
{
@@ -55,6 +58,18 @@
return "TI AR7 (TNETD7100)";
case AR7_CHIP_7200:
return "TI AR7 (TNETD7200)";
+ case AR7_CHIP_TITAN:
+ titan_variant = ar7_init_titan_variant();
+ switch (titan_variant /*(gpio_get_value_titan(1) >> 12) & 0xf*/) {
+ case TITAN_CHIP_1050:
+ return "TI AR7 (TNETV1050)";
+ case TITAN_CHIP_1055:
+ return "TI AR7 (TNETV1055)";
+ case TITAN_CHIP_1056:
+ return "TI AR7 (TNETV1056)";
+ case TITAN_CHIP_1060:
+ return "TI AR7 (TNETV1060)";
+ }
default:
return "TI AR7 (Unknown)";
}
Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar7/ar7.h
===================================================================
--- linux-2.6.32.7.orig/arch/mips/include/asm/mach-ar7/ar7.h 2010-01-29 00:06:20.000000000 +0100
+++ linux-2.6.32.7/arch/mips/include/asm/mach-ar7/ar7.h 2010-02-04 14:33:24.000000000 +0100
@@ -50,6 +50,11 @@
#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
+#define TITAN_REGS_MAC0 (0x08640000)
+#define TITAN_REGS_MAC1 (TITAN_REGS_MAC0 + 0x0800)
+#define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00)
+#define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300)
+
#define AR7_RESET_PEREPHERIAL 0x0
#define AR7_RESET_SOFTWARE 0x4
#define AR7_RESET_STATUS 0x8
@@ -59,15 +64,30 @@
#define AR7_RESET_BIT_MDIO 22
#define AR7_RESET_BIT_EPHY 26
+#define TITAN_RESET_BIT_EPHY1 28
+
/* GPIO control registers */
#define AR7_GPIO_INPUT 0x0
#define AR7_GPIO_OUTPUT 0x4
#define AR7_GPIO_DIR 0x8
#define AR7_GPIO_ENABLE 0xc
+#define TITAN_GPIO_INPUT_0 0x0
+#define TITAN_GPIO_INPUT_1 0x4
+#define TITAN_GPIO_OUTPUT_0 0x8
+#define TITAN_GPIO_OUTPUT_1 0xc
+#define TITAN_GPIO_DIR_0 0x10
+#define TITAN_GPIO_DIR_1 0x14
+#define TITAN_GPIO_ENBL_0 0x18
+#define TITAN_GPIO_ENBL_1 0x1c
#define AR7_CHIP_7100 0x18
#define AR7_CHIP_7200 0x2b
#define AR7_CHIP_7300 0x05
+#define AR7_CHIP_TITAN 0x07
+#define TITAN_CHIP_1050 0x0f
+#define TITAN_CHIP_1055 0x0e
+#define TITAN_CHIP_1056 0x0d
+#define TITAN_CHIP_1060 0x07
/* Interrupts */
#define AR7_IRQ_UART0 15
@@ -95,14 +115,22 @@
extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
+static inline int ar7_is_titan(void)
+{
+ return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
+ AR7_CHIP_TITAN;
+}
+
static inline u16 ar7_chip_id(void)
{
- return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
+ return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
+ KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
}
static inline u8 ar7_chip_rev(void)
{
- return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
+ return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
+ 0x14))) >> 16) & 0xff;
}
static inline int ar7_cpu_freq(void)
Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar7/gpio.h
===================================================================
--- linux-2.6.32.7.orig/arch/mips/include/asm/mach-ar7/gpio.h 2010-01-29 00:06:20.000000000 +0100
+++ linux-2.6.32.7/arch/mips/include/asm/mach-ar7/gpio.h 2010-02-04 14:39:21.000000000 +0100
@@ -20,14 +20,18 @@
#define __AR7_GPIO_H__
#include <asm/mach-ar7/ar7.h>
+#ifndef __AR7_TITAN_H__
+#include <asm/mach-ar7/titan.h>
+#endif
#define AR7_GPIO_MAX 32
+#define TITAN_GPIO_MAX 51
extern int gpio_request(unsigned gpio, const char *label);
extern void gpio_free(unsigned gpio);
/* Common GPIO layer */
-static inline int gpio_get_value(unsigned gpio)
+static inline int gpio_get_value_ar7(unsigned gpio)
{
void __iomem *gpio_in =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT);
@@ -35,7 +39,23 @@
return readl(gpio_in) & (1 << gpio);
}
-static inline void gpio_set_value(unsigned gpio, int value)
+static inline int gpio_get_value_titan(unsigned gpio)
+{
+ void __iomem *gpio_in0 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
+ void __iomem *gpio_in1 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_1);
+
+ return readl(gpio >> 5 ? gpio_in1 : gpio_in0) & (1 << (gpio & 0x1f));
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+ return ar7_is_titan() ? gpio_get_value_titan(gpio) :
+ gpio_get_value_ar7(gpio);
+}
+
+static inline void gpio_set_value_ar7(unsigned gpio, int value)
{
void __iomem *gpio_out =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT);
@@ -47,7 +67,29 @@
writel(tmp, gpio_out);
}
-static inline int gpio_direction_input(unsigned gpio)
+static inline void gpio_set_value_titan(unsigned gpio, int value)
+{
+ void __iomem *gpio_out0 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_0);
+ void __iomem *gpio_out1 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_OUTPUT_1);
+ unsigned tmp;
+
+ tmp = readl(gpio >> 5 ? gpio_out1 : gpio_out0) & ~(1 << (gpio & 0x1f));
+ if (value)
+ tmp |= 1 << (gpio & 0x1f);
+ writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+ if (ar7_is_titan())
+ gpio_set_value_titan(gpio, value);
+ else
+ gpio_set_value_ar7(gpio, value);
+}
+
+static inline int gpio_direction_input_ar7(unsigned gpio)
{
void __iomem *gpio_dir =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
@@ -60,7 +102,29 @@
return 0;
}
-static inline int gpio_direction_output(unsigned gpio, int value)
+static inline int gpio_direction_input_titan(unsigned gpio)
+{
+ void __iomem *gpio_dir0 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0);
+ void __iomem *gpio_dir1 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1);
+
+ if (gpio >= TITAN_GPIO_MAX)
+ return -EINVAL;
+
+ writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)),
+ gpio >> 5 ? gpio_dir1 : gpio_dir0);
+
+ return 0;
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+ return ar7_is_titan() ? gpio_direction_input_titan(gpio) :
+ gpio_direction_input_ar7(gpio);
+}
+
+static inline int gpio_direction_output_ar7(unsigned gpio, int value)
{
void __iomem *gpio_dir =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
@@ -74,6 +138,29 @@
return 0;
}
+static inline int gpio_direction_output_titan(unsigned gpio, int value)
+{
+ void __iomem *gpio_dir0 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_0);
+ void __iomem *gpio_dir1 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_DIR_1);
+
+ if (gpio >= TITAN_GPIO_MAX)
+ return -EINVAL;
+
+ gpio_set_value_titan(gpio, value);
+ writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 <<
+ (gpio & 0x1f)), gpio >> 5 ? gpio_dir1 : gpio_dir0);
+
+ return 0;
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+ return ar7_is_titan() ? gpio_direction_output_titan(gpio, value) :
+ gpio_direction_output_ar7(gpio, value);
+}
+
static inline int gpio_to_irq(unsigned gpio)
{
return -EINVAL;
@@ -85,7 +172,7 @@
}
/* Board specific GPIO functions */
-static inline int ar7_gpio_enable(unsigned gpio)
+static inline int ar7_gpio_enable_ar7(unsigned gpio)
{
void __iomem *gpio_en =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
@@ -95,7 +182,26 @@
return 0;
}
-static inline int ar7_gpio_disable(unsigned gpio)
+static inline int ar7_gpio_enable_titan(unsigned gpio)
+{
+ void __iomem *gpio_en0 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0);
+ void __iomem *gpio_en1 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1);
+
+ writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)),
+ gpio >> 5 ? gpio_en1 : gpio_en0);
+
+ return 0;
+}
+
+static inline int ar7_gpio_enable(unsigned gpio)
+{
+ return ar7_is_titan() ? ar7_gpio_enable_titan(gpio) :
+ ar7_gpio_enable_ar7(gpio);
+}
+
+static inline int ar7_gpio_disable_ar7(unsigned gpio)
{
void __iomem *gpio_en =
(void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
@@ -105,6 +211,60 @@
return 0;
}
+static inline int ar7_gpio_disable_titan(unsigned gpio)
+{
+ void __iomem *gpio_en0 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_0);
+ void __iomem *gpio_en1 =
+ (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_ENBL_1);
+
+ writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)),
+ gpio >> 5 ? gpio_en1 : gpio_en0);
+
+ return 0;
+}
+
+static inline int ar7_gpio_disable(unsigned gpio)
+{
+ return ar7_is_titan() ? ar7_gpio_disable_titan(gpio) :
+ ar7_gpio_disable_ar7(gpio);
+}
+
+static inline int ar7_init_titan_variant(void)
+{
+ /*UINT32 new_val;*/
+ unsigned new_val;
+
+ /* set GPIO 44 - 47 as input */
+ /*PAL_sysGpioCtrl(const int, GPIO_PIN, GPIO_INPUT_PIN); */
+ /*define titan_gpio_ctrl in titan.h*/
+ titan_gpio_ctrl(44, GPIO_PIN, GPIO_INPUT_PIN);
+ titan_gpio_ctrl(45, GPIO_PIN, GPIO_INPUT_PIN);
+ titan_gpio_ctrl(46, GPIO_PIN, GPIO_INPUT_PIN);
+ titan_gpio_ctrl(47, GPIO_PIN, GPIO_INPUT_PIN);
+
+ /* read GPIO to get Titan variant type */
+ /*fix this*/
+ titan_sysGpioInValue( &new_val, 1 );
+
+ new_val >>= 12;
+ new_val &= 0x0f;
+
+ switch ( new_val )
+ {
+ case TITAN_CHIP_1050:
+ case TITAN_CHIP_1055:
+ case TITAN_CHIP_1056:
+ case TITAN_CHIP_1060:
+ return new_val;
+
+ default:
+ break;
+ }
+ /* In case we get an invalid value, return the default Titan chip */
+ return TITAN_CHIP_1050;
+}
+
#include <asm-generic/gpio.h>
#endif
Index: linux-2.6.32.7/arch/mips/include/asm/mach-ar7/titan.h
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-2.6.32.7/arch/mips/include/asm/mach-ar7/titan.h 2010-02-04 14:40:44.000000000 +0100
@@ -0,0 +1,176 @@
+/*
+ * Copyright (C) 2008 Stanley Pinchak <stanley_dot_pinchak_at_gmail_dot_com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#ifndef __AR7_TITAN_H__
+#define __AR7_TITAN_H__
+
+#include <asm/mach-ar7/gpio.h>
+
+typedef enum TITAN_GPIO_PIN_MODE_tag
+{
+ FUNCTIONAL_PIN = 0,
+ GPIO_PIN = 1
+} TITAN_GPIO_PIN_MODE_T;
+
+typedef enum TITAN_GPIO_PIN_DIRECTION_tag
+{
+ GPIO_OUTPUT_PIN = 0,
+ GPIO_INPUT_PIN = 1
+} TITAN_GPIO_PIN_DIRECTION_T;
+
+/**********************************************************************
+ * GPIO Control
+ **********************************************************************/
+
+typedef struct
+{
+ int pinSelReg;
+ int shift;
+ int func;
+
+} GPIO_CFG;
+
+static GPIO_CFG gptable[]= {
+ /* PIN_SEL_REG, START_BIT, GPIO_CFG_MUX_VALUE */
+ {4,24,1},
+ {4,26,1},
+ {4,28,1},
+ {4,30,1},
+ {5,6,1},
+ {5,8,1},
+ {5,10,1},
+ {5,12,1},
+ {7,14,3},
+ {7,16,3},
+ {7,18,3},
+ {7,20,3},
+ {7,22,3},
+ {7,26,3},
+ {7,28,3},
+ {7,30,3},
+ {8,0,3},
+ {8,2,3},
+ {8,4,3},
+ {8,10,3},
+ {8,14,3},
+ {8,16,3},
+ {8,18,3},
+ {8,20,3},
+ {9,8,3},
+ {9,10,3},
+ {9,12,3},
+ {9,14,3},
+ {9,18,3},
+ {9,20,3},
+ {9,24,3},
+ {9,26,3},
+ {9,28,3},
+ {9,30,3},
+ {10,0,3},
+ {10,2,3},
+ {10,8,3},
+ {10,10,3},
+ {10,12,3},
+ {10,14,3},
+ {13,12,3},
+ {13,14,3},
+ {13,16,3},
+ {13,18,3},
+ {13,24,3},
+ {13,26,3},
+ {13,28,3},
+ {13,30,3},
+ {14,2,3},
+ {14,6,3},
+ {14,8,3},
+ {14,12,3}
+};
+
+typedef struct
+{
+ volatile unsigned int reg[21];
+}
+PIN_SEL_REG_ARRAY_T;
+
+typedef struct
+{
+ unsigned int data_in [2];
+ unsigned int data_out[2];
+ unsigned int dir[2];
+ unsigned int enable[2];
+
+} TITAN_GPIO_CONTROL_T;
+
+#define AVALANCHE_PIN_SEL_BASE 0xA861160C /*replace with KSEG1ADDR()*/
+
+static inline int titan_gpio_ctrl(unsigned int gpio_pin, TITAN_GPIO_PIN_MODE_T pin_mode,
+ TITAN_GPIO_PIN_DIRECTION_T pin_direction)
+{
+ int reg_index = 0;
+ int mux_status;
+ GPIO_CFG gpio_cfg;
+ volatile PIN_SEL_REG_ARRAY_T *pin_sel_array = (PIN_SEL_REG_ARRAY_T*) AVALANCHE_PIN_SEL_BASE;
+ volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
+
+ if (gpio_pin > 51 )
+ return(-1);
+
+ gpio_cfg = gptable[gpio_pin];
+ mux_status = (pin_sel_array->reg[gpio_cfg.pinSelReg - 1] >> gpio_cfg.shift) & 0x3;
+ if(!((mux_status == 0 /* tri-stated */ ) || (mux_status == gpio_cfg.func /*GPIO functionality*/)))
+ {
+ return(-1); /* Pin have been configured for non GPIO funcs. */
+ }
+
+ /* Set the pin to be used as GPIO. */
+ pin_sel_array->reg[gpio_cfg.pinSelReg - 1] |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
+
+ /* Check whether gpio refers to the first GPIO reg or second. */
+ if(gpio_pin > 31)
+ {
+ reg_index = 1;
+ gpio_pin -= 32;
+ }
+
+ if(pin_mode)
+ gpio_cntl->enable[reg_index] |= (1 << gpio_pin); /* Enable */
+ else
+ gpio_cntl->enable[reg_index] &= ~(1 << gpio_pin);
+
+ if(pin_direction)
+ gpio_cntl->dir[reg_index] |= (1 << gpio_pin); /* Input */
+ else
+ gpio_cntl->dir[reg_index] &= ~(1 << gpio_pin);
+
+ return(0);
+
+}/* end of function titan_gpio_ctrl */
+
+static inline int titan_sysGpioInValue(unsigned int *in_val, unsigned int reg_index)
+{
+ volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
+
+ if(reg_index > 1)
+ return (-1);
+
+ *in_val = gpio_cntl->data_in[reg_index];
+
+ return (0);
+}
+
+
+#endif

72
target/linux/ar7/patches-2.6.32/940-cpmac-titan.patch Normal file
View File

@ -0,0 +1,72 @@
Index: linux-2.6.32.7/arch/mips/ar7/platform.c
===================================================================
--- linux-2.6.32.7.orig/arch/mips/ar7/platform.c 2010-02-04 14:00:53.000000000 +0100
+++ linux-2.6.32.7/arch/mips/ar7/platform.c 2010-02-04 14:14:21.000000000 +0100
@@ -716,23 +716,35 @@
}
if (ar7_has_high_cpmac()) {
- res = fixed_phy_add(PHY_POLL, cpmac_high.id, &fixed_phy_status);
+ res = fixed_phy_add(PHY_POLL, ar7_is_titan() ? cpmac_high_titan.id : cpmac_high.id,
+ &fixed_phy_status);
if (res && res != -ENODEV)
return res;
- cpmac_get_mac(1, cpmac_high_data.dev_addr);
- res = platform_device_register(&cpmac_high);
+
+ cpmac_get_mac(1, ar7_is_titan() ? cpmac_high_data_titan.dev_addr :
+ cpmac_high_data.dev_addr);
+ res = platform_device_register(ar7_is_titan() ? &cpmac_high_titan :
+ &cpmac_high);
+
if (res)
return res;
} else {
- cpmac_low_data.phy_mask = 0xffffffff;
+ if (ar7_is_titan())
+ cpmac_low_data_titan.phy_mask = 0xffffffff;
+ else
+ cpmac_low_data.phy_mask = 0xffffffff;
+
}
- res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status);
+ res = fixed_phy_add(PHY_POLL, ar7_is_titan() ? cpmac_low_titan.id :
+ cpmac_low.id, &fixed_phy_status);
if (res && res != -ENODEV)
return res;
- cpmac_get_mac(0, cpmac_low_data.dev_addr);
- res = platform_device_register(&cpmac_low);
+ cpmac_get_mac(0, ar7_is_titan() ? cpmac_low_data_titan.dev_addr :
+ cpmac_low_data.dev_addr);
+ res = platform_device_register(ar7_is_titan() ? &cpmac_low_titan :
+ &cpmac_low);
if (res)
return res;
Index: linux-2.6.32.7/drivers/net/cpmac.c
===================================================================
--- linux-2.6.32.7.orig/drivers/net/cpmac.c 2010-01-29 00:06:20.000000000 +0100
+++ linux-2.6.32.7/drivers/net/cpmac.c 2010-02-04 14:05:24.000000000 +0100
@@ -1243,6 +1243,10 @@
ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
ar7_device_reset(AR7_RESET_BIT_EPHY);
+ if (ar7_is_titan()) {
+ ar7_device_reset(TITAN_RESET_BIT_EPHY1);
+ }
+
cpmac_mii->reset(cpmac_mii);
for (i = 0; i < 300; i++)
@@ -1257,7 +1261,8 @@
mask = 0;
}
- cpmac_mii->phy_mask = ~(mask | 0x80000000);
+ cpmac_mii->phy_mask = ar7_is_titan()? ~(mask | 0x80000000 | 0x40000000):
+ ~(mask | 0x80000000);
snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "1");
res = mdiobus_register(cpmac_mii);