mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-11-04 06:54:27 -05:00
layerscape: copy patches 5.10 to 5.15
One patch manually rebased: 302-arm64-dts-ls1012a-update-with-ppfe-support.patch PFE driver patch recreated from NXP 5.15 tree: 701-staging-add-fsl_ppfe-driver.patch Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
This commit is contained in:
Pawel Dembicki
Hauke Mehrtens
parent
f620fb4b73
commit
8efffce677
@ -0,0 +1,26 @@
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From 5b35aae22b4ca2400e49561c9267aa01346f91d4 Mon Sep 17 00:00:00 2001
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From: Mathew McBride <matt@traverse.com.au>
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Date: Tue, 17 Apr 2018 10:01:03 +1000
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Subject: [PATCH] add DTS for Traverse LS1043 Boards
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Signed-off-by: Mathew McBride <matt@traverse.com.au>
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[rebase]
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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arch/arm64/boot/dts/freescale/Makefile | 3 +++
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arch/arm64/boot/dts/freescale/traverse-ls1043s.dts | 29 ++++++++++++++++++++++
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arch/arm64/boot/dts/freescale/traverse-ls1043v.dts | 29 ++++++++++++++++++++++
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3 files changed, 61 insertions(+)
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--- a/arch/arm64/boot/dts/freescale/Makefile
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+++ b/arch/arm64/boot/dts/freescale/Makefile
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@@ -31,6 +31,9 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb
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+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043v.dtb
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+dtb-$(CONFIG_ARCH_LAYERSCAPE) += traverse-ls1043s.dtb
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+
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
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@ -0,0 +1,291 @@
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From 55e00e402d6143aeb153761f8144d9fee5f1f009 Mon Sep 17 00:00:00 2001
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From: Biwen Li <biwen.li@nxp.com>
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Date: Fri, 26 Oct 2018 16:00:37 +0800
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Subject: [PATCH] arm: dts: ls1021a: Add LS1021A-IOT board support
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Signed-off-by: Biwen Li <biwen.li@nxp.com>
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[rebase]
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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arch/arm/boot/dts/Makefile | 3 +-
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arch/arm/boot/dts/ls1021a-iot.dts | 262 ++++++++++++++++++++++++++++++++++++++
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2 files changed, 264 insertions(+), 1 deletion(-)
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create mode 100644 arch/arm/boot/dts/ls1021a-iot.dts
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -713,7 +713,8 @@ dtb-$(CONFIG_SOC_LS1021A) += \
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ls1021a-moxa-uc-8410a.dtb \
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ls1021a-qds.dtb \
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ls1021a-tsn.dtb \
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- ls1021a-twr.dtb
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+ ls1021a-twr.dtb \
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+ ls1021a-iot.dtb
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dtb-$(CONFIG_SOC_VF610) += \
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vf500-colibri-eval-v3.dtb \
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vf610-bk4.dtb \
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--- /dev/null
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+++ b/arch/arm/boot/dts/ls1021a-iot.dts
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@@ -0,0 +1,262 @@
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+/*
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+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ */
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+
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+/dts-v1/;
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+#include "ls1021a.dtsi"
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+
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+/ {
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+ model = "LS1021A IOT Board";
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+
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+ sys_mclk: clock-mclk {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <24576000>;
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+ };
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+
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+ regulators {
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+ compatible = "simple-bus";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ reg_3p3v: regulator@0 {
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+ compatible = "regulator-fixed";
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+ reg = <0>;
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+ regulator-name = "3P3V";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-always-on;
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+ };
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+
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+ reg_2p5v: regulator@1 {
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+ compatible = "regulator-fixed";
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+ reg = <1>;
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+ regulator-name = "2P5V";
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+ regulator-min-microvolt = <2500000>;
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+ regulator-max-microvolt = <2500000>;
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+ regulator-always-on;
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+ };
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+ };
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+
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+ sound {
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+ compatible = "simple-audio-card";
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+ simple-audio-card,format = "i2s";
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+ simple-audio-card,widgets =
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+ "Microphone", "Microphone Jack",
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+ "Headphone", "Headphone Jack",
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+ "Speaker", "Speaker Ext",
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+ "Line", "Line In Jack";
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+ simple-audio-card,routing =
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+ "MIC_IN", "Microphone Jack",
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+ "Microphone Jack", "Mic Bias",
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+ "LINE_IN", "Line In Jack",
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+ "Headphone Jack", "HP_OUT",
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+ "Speaker Ext", "LINE_OUT";
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+
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+ simple-audio-card,cpu {
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+ sound-dai = <&sai2>;
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+ frame-master;
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+ bitclock-master;
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+ };
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+
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+ simple-audio-card,codec {
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+ sound-dai = <&codec>;
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+ frame-master;
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+ bitclock-master;
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+ };
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+ };
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+
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+ firmware {
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+ optee {
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+ compatible = "linaro,optee-tz";
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+ method = "smc";
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+ };
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+ };
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+};
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+
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+&enet0 {
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+ tbi-handle = <&tbi1>;
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+ phy-handle = <&phy1>;
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+ phy-connection-type = "sgmii";
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+ status = "okay";
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+};
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+
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+&enet1 {
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+ tbi-handle = <&tbi1>;
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+ phy-handle = <&phy3>;
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+ phy-connection-type = "sgmii";
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+ status = "okay";
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+};
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+
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+&enet2 {
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+ fixed-link = <0 1 1000 0 0>;
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+ phy-connection-type = "rgmii-id";
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+ status = "okay";
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+};
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+
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+&can0{
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+ status = "disabled";
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+};
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+
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+&can1{
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+ status = "disabled";
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+};
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+
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+&can2{
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+ status = "disabled";
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+};
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+
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+&can3{
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+ status = "okay";
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+};
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+
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+&esdhc{
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+
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+ max1239@35 {
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+ compatible = "maxim,max1239";
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+ reg = <0x35>;
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+ #io-channel-cells = <1>;
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+ };
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+
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+ codec: sgtl5000@2a {
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+ #sound-dai-cells=<0x0>;
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+ compatible = "fsl,sgtl5000";
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+ reg = <0x2a>;
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+ VDDA-supply = <®_3p3v>;
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+ VDDIO-supply = <®_2p5v>;
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+ clocks = <&sys_mclk 1>;
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+ };
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+
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+ pca9555: pca9555@23 {
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+ compatible = "nxp,pca9555";
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+ /*pinctrl-names = "default";*/
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+ /*interrupt-parent = <&gpio2>;
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+ interrupts = <19 0x2>;*/
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ reg = <0x23>;
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+ };
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+
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+ ina220@44 {
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+ compatible = "ti,ina220";
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+ reg = <0x44>;
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+ shunt-resistor = <1000>;
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+ };
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+
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+ ina220@45 {
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+ compatible = "ti,ina220";
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+ reg = <0x45>;
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+ shunt-resistor = <1000>;
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+ };
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+
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+ lm75b@48 {
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+ compatible = "nxp,lm75a";
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+ reg = <0x48>;
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+ };
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+
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+ adt7461a@4c {
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+ compatible = "adt7461a";
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+ reg = <0x4c>;
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+ };
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+
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+ hdmi: sii9022a@39 {
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+ compatible = "fsl,sii902x";
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+ reg = <0x39>;
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+ interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
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+ };
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+};
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+
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+&i2c1 {
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+ status = "disabled";
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+};
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+
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+&ifc {
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+ status = "disabled";
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+};
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+
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+&lpuart0 {
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+ status = "okay";
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+};
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+
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+&mdio0 {
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+ phy0: ethernet-phy@0 {
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+ reg = <0x0>;
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+ };
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+ phy1: ethernet-phy@1 {
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+ reg = <0x1>;
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+ };
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+ phy2: ethernet-phy@2 {
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+ reg = <0x2>;
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+ };
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+ phy3: ethernet-phy@3 {
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+ reg = <0x3>;
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+ };
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+ tbi1: tbi-phy@1f {
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+ reg = <0x1f>;
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+ device_type = "tbi-phy";
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+ };
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+};
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+
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+&qspi {
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+ num-cs = <2>;
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+ status = "okay";
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+
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+ qflash0: s25fl128s@0 {
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+ compatible = "spansion,s25fl129p1";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ spi-max-frequency = <20000000>;
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+ reg = <0>;
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+ };
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+};
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+
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+&sai2 {
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+ status = "okay";
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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+
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+&uart1 {
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+ status = "okay";
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+};
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+
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+&dcu {
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+ display = <&display>;
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+ status = "okay";
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+
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+ display: display@0 {
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+ bits-per-pixel = <24>;
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+
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+ display-timings {
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+ native-mode = <&timing0>;
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+
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+ timing0: mode0 {
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+ clock-frequency = <25000000>;
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+ hactive = <640>;
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+ vactive = <480>;
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+ hback-porch = <80>;
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+ hfront-porch = <80>;
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+ vback-porch = <16>;
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+ vfront-porch = <16>;
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+ hsync-len = <12>;
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+ vsync-len = <2>;
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+ hsync-active = <1>;
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+ vsync-active = <1>;
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+ };
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+ };
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+ };
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+};
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@ -0,0 +1,288 @@
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From 1bb35ff4ce33e65601c8d9c736be52e4aabd6252 Mon Sep 17 00:00:00 2001
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From: Calvin Johnson <calvin.johnson@nxp.com>
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Date: Sat, 16 Sep 2017 14:20:23 +0530
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Subject: [PATCH] arm64: dts: freescale: ls1012a: update with ppfe support
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|
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Update ls1012a dtsi and platform dts files with support for ppfe.
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Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
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Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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---
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.../boot/dts/freescale/fsl-ls1012a-frdm.dts | 43 +++++++++++++++++
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.../boot/dts/freescale/fsl-ls1012a-frwy.dts | 43 +++++++++++++++++
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.../boot/dts/freescale/fsl-ls1012a-qds.dts | 43 +++++++++++++++++
|
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.../boot/dts/freescale/fsl-ls1012a-rdb.dts | 47 +++++++++++++++++++
|
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.../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 29 ++++++++++++
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5 files changed, 205 insertions(+)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
|
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
|
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@@ -14,6 +14,11 @@
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model = "LS1012A Freedom Board";
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compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
|
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|
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+ aliases {
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+ ethernet0 = &pfe_mac0;
|
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+ ethernet1 = &pfe_mac1;
|
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+ };
|
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+
|
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sys_mclk: clock-mclk {
|
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compatible = "fixed-clock";
|
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#clock-cells = <0>;
|
||||
@@ -95,6 +100,44 @@
|
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};
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};
|
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|
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+&pfe {
|
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+ status = "okay";
|
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+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ pfe_mac0: ethernet@0 {
|
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+ compatible = "fsl,pfe-gemac-port";
|
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+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0x0>; /* GEM_ID */
|
||||
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
|
||||
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
|
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+ fsl,mdio-mux-val = <0x0>;
|
||||
+ phy-mode = "sgmii";
|
||||
+ fsl,pfe-phy-if-flags = <0x0>;
|
||||
+
|
||||
+ mdio@0 {
|
||||
+ reg = <0x1>; /* enabled/disabled */
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pfe_mac1: ethernet@1 {
|
||||
+ compatible = "fsl,pfe-gemac-port";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0x1>; /* GEM_ID */
|
||||
+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
|
||||
+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
|
||||
+ fsl,mdio-mux-val = <0x0>;
|
||||
+ phy-mode = "sgmii";
|
||||
+ fsl,pfe-phy-if-flags = <0x0>;
|
||||
+
|
||||
+ mdio@0 {
|
||||
+ reg = <0x0>; /* enabled/disabled */
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
|
||||
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
|
||||
@@ -14,6 +14,11 @@
|
||||
/ {
|
||||
model = "LS1012A FRWY Board";
|
||||
compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet0 = &pfe_mac0;
|
||||
+ ethernet1 = &pfe_mac1;
|
||||
+ };
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
@@ -28,6 +33,44 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&pfe {
|
||||
+ status = "okay";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ pfe_mac0: ethernet@0 {
|
||||
+ compatible = "fsl,pfe-gemac-port";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0x0>; /* GEM_ID */
|
||||
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
|
||||
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
|
||||
+ fsl,mdio-mux-val = <0x0>;
|
||||
+ phy-mode = "sgmii";
|
||||
+ fsl,pfe-phy-if-flags = <0x0>;
|
||||
+
|
||||
+ mdio@0 {
|
||||
+ reg = <0x1>; /* enabled/disabled */
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pfe_mac1: ethernet@1 {
|
||||
+ compatible = "fsl,pfe-gemac-port";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0x1>; /* GEM_ID */
|
||||
+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
|
||||
+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
|
||||
+ fsl,mdio-mux-val = <0x0>;
|
||||
+ phy-mode = "sgmii";
|
||||
+ fsl,pfe-phy-if-flags = <0x0>;
|
||||
+
|
||||
+ mdio@0 {
|
||||
+ reg = <0x0>; /* enabled/disabled */
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
|
||||
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
|
||||
@@ -18,6 +18,11 @@
|
||||
mmc1 = &esdhc1;
|
||||
};
|
||||
|
||||
+ aliases {
|
||||
+ ethernet0 = &pfe_mac0;
|
||||
+ ethernet1 = &pfe_mac1;
|
||||
+ };
|
||||
+
|
||||
sys_mclk: clock-mclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
@@ -132,6 +137,44 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+&pfe {
|
||||
+ status = "okay";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ pfe_mac0: ethernet@0 {
|
||||
+ compatible = "fsl,pfe-gemac-port";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0x0>; /* GEM_ID */
|
||||
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
|
||||
+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */
|
||||
+ fsl,mdio-mux-val = <0x2>;
|
||||
+ phy-mode = "sgmii-2500";
|
||||
+ fsl,pfe-phy-if-flags = <0x0>;
|
||||
+
|
||||
+ mdio@0 {
|
||||
+ reg = <0x1>; /* enabled/disabled */
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pfe_mac1: ethernet@1 {
|
||||
+ compatible = "fsl,pfe-gemac-port";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0x1>; /* GEM_ID */
|
||||
+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
|
||||
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
|
||||
+ fsl,mdio-mux-val = <0x3>;
|
||||
+ phy-mode = "sgmii-2500";
|
||||
+ fsl,pfe-phy-if-flags = <0x0>;
|
||||
+
|
||||
+ mdio@0 {
|
||||
+ reg = <0x0>; /* enabled/disabled */
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
|
||||
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
|
||||
@@ -16,6 +16,8 @@
|
||||
|
||||
aliases {
|
||||
serial0 = &duart0;
|
||||
+ ethernet0 = &pfe_mac0;
|
||||
+ ethernet1 = &pfe_mac1;
|
||||
mmc0 = &esdhc0;
|
||||
mmc1 = &esdhc1;
|
||||
};
|
||||
@@ -86,6 +88,44 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&pfe {
|
||||
+ status = "okay";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ pfe_mac0: ethernet@0 {
|
||||
+ compatible = "fsl,pfe-gemac-port";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0x0>; /* GEM_ID */
|
||||
+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
|
||||
+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */
|
||||
+ fsl,mdio-mux-val = <0x0>;
|
||||
+ phy-mode = "sgmii";
|
||||
+ fsl,pfe-phy-if-flags = <0x0>;
|
||||
+
|
||||
+ mdio@0 {
|
||||
+ reg = <0x1>; /* enabled/disabled */
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pfe_mac1: ethernet@1 {
|
||||
+ compatible = "fsl,pfe-gemac-port";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0x1>; /* GEM_ID */
|
||||
+ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
|
||||
+ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
|
||||
+ fsl,mdio-mux-val = <0x0>;
|
||||
+ phy-mode = "rgmii-txid";
|
||||
+ fsl,pfe-phy-if-flags = <0x0>;
|
||||
+
|
||||
+ mdio@0 {
|
||||
+ reg = <0x0>; /* enabled/disabled */
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
|
||||
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
|
||||
@@ -560,6 +560,35 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ reserved-memory {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ ranges;
|
||||
+
|
||||
+ pfe_reserved: packetbuffer@83400000 {
|
||||
+ reg = <0 0x83400000 0 0xc00000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pfe: pfe@04000000 {
|
||||
+ compatible = "fsl,pfe";
|
||||
+ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
|
||||
+ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
|
||||
+ reg-names = "pfe", "pfe-ddr";
|
||||
+ fsl,pfe-num-interfaces = <0x2>;
|
||||
+ interrupts = <0 172 0x4>, /* HIF interrupt */
|
||||
+ <0 173 0x4>, /*HIF_NOCPY interrupt */
|
||||
+ <0 174 0x4>; /* WoL interrupt */
|
||||
+ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
|
||||
+ memory-region = <&pfe_reserved>;
|
||||
+ fsl,pfe-scfg = <&scfg 0>;
|
||||
+ fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
|
||||
+ clocks = <&clockgen 4 0>;
|
||||
+ clock-names = "pfe";
|
||||
+
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
@ -0,0 +1,41 @@
|
||||
From 9c5c18dbf8e1845d349ef7020f8af5bc9b56ed1f Mon Sep 17 00:00:00 2001
|
||||
From: Pawel Dembicki <paweldembicki@gmail.com>
|
||||
Date: Fri, 28 Sep 2022 17:14:32 +0200
|
||||
Subject: [PATCH] arm64: dts: ls1012a-frdm/qds: workaround by updating qspi flash to
|
||||
single mode
|
||||
|
||||
Update rx and tx bus-width to 1 to use single mode to workaround ubifs
|
||||
issue found with double mode. (The same method as RDB board)
|
||||
|
||||
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 4 ++--
|
||||
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 4 ++--
|
||||
2 file changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
|
||||
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
|
||||
@@ -148,8 +148,8 @@
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
reg = <0>;
|
||||
- spi-rx-bus-width = <2>;
|
||||
- spi-tx-bus-width = <2>;
|
||||
+ spi-rx-bus-width = <1>;
|
||||
+ spi-tx-bus-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
|
||||
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
|
||||
@@ -186,8 +186,8 @@
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
reg = <0>;
|
||||
- spi-rx-bus-width = <2>;
|
||||
- spi-tx-bus-width = <2>;
|
||||
+ spi-rx-bus-width = <1>;
|
||||
+ spi-tx-bus-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -0,0 +1,29 @@
|
||||
From 9c5c18dbf8e1845d349ef7020f8af5bc9b56ed1f Mon Sep 17 00:00:00 2001
|
||||
From: Kuldeep Singh <kuldeep.singh@nxp.com>
|
||||
Date: Tue, 7 Jan 2020 17:14:32 +0530
|
||||
Subject: [PATCH] arm64: dts: ls1012a-rdb: workaround by updating qspi flash to
|
||||
single mode
|
||||
|
||||
Update rx and tx bus-width to 1 to use single mode to workaround ubifs
|
||||
issue found with double mode.
|
||||
|
||||
[ Leo: Local workaround ]
|
||||
|
||||
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
|
||||
---
|
||||
arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
|
||||
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
|
||||
@@ -136,8 +136,8 @@
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
reg = <0>;
|
||||
- spi-rx-bus-width = <2>;
|
||||
- spi-tx-bus-width = <2>;
|
||||
+ spi-rx-bus-width = <1>;
|
||||
+ spi-tx-bus-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -0,0 +1,34 @@
|
||||
From 38093ebbf25eb60a1aa863f46118a68a0300c56e Mon Sep 17 00:00:00 2001
|
||||
From: Kuldeep Singh <kuldeep.singh@nxp.com>
|
||||
Date: Fri, 3 Jan 2020 14:49:07 +0530
|
||||
Subject: [PATCH] arm64: dts: ls1046a-rdb: Update qspi spi-rx-bus-width to 1
|
||||
|
||||
Update rx width from quad mode to single mode as a workaround.
|
||||
|
||||
[Leo: Local workaround ]
|
||||
|
||||
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
|
||||
---
|
||||
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
|
||||
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
|
||||
@@ -104,7 +104,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
- spi-rx-bus-width = <4>;
|
||||
+ spi-rx-bus-width = <1>;
|
||||
spi-tx-bus-width = <1>;
|
||||
reg = <0>;
|
||||
};
|
||||
@@ -114,7 +114,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
- spi-rx-bus-width = <4>;
|
||||
+ spi-rx-bus-width = <1>;
|
||||
spi-tx-bus-width = <1>;
|
||||
reg = <1>;
|
||||
};
|
||||
@ -0,0 +1,26 @@
|
||||
From 2b84e88d36de482da0370290ad4af09a71993f08 Mon Sep 17 00:00:00 2001
|
||||
From: Han Xu <han.xu@nxp.com>
|
||||
Date: Tue, 14 Apr 2020 11:58:44 -0500
|
||||
Subject: [PATCH] LF-20-3 mtd: spi-nor: Use 1 bit mode of spansion(s25fs512s)
|
||||
flash
|
||||
|
||||
This is a workaround patch which uses only single bit mode of s25fs512s
|
||||
flash
|
||||
|
||||
Signed-off-by: Han Xu <han.xu@nxp.com>
|
||||
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
|
||||
---
|
||||
drivers/mtd/spi-nor/spansion.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/mtd/spi-nor/spansion.c
|
||||
+++ b/drivers/mtd/spi-nor/spansion.c
|
||||
@@ -227,7 +227,7 @@ static const struct flash_info spansion_
|
||||
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
|
||||
USE_CLSR) },
|
||||
{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256,
|
||||
- SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR)
|
||||
+ SPI_NOR_4B_OPCODES | USE_CLSR)
|
||||
.fixups = &s25fs_s_fixups, },
|
||||
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
|
||||
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,32 @@
|
||||
From c918c472546afa83a619ae3cb1a9d7d346c6e288 Mon Sep 17 00:00:00 2001
|
||||
From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
|
||||
Date: Wed, 29 Nov 2017 15:27:57 +0530
|
||||
Subject: [PATCH 154/173] phy: Add 2.5G SGMII interface mode
|
||||
|
||||
Add 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII)
|
||||
in existing phy_interface list
|
||||
|
||||
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
|
||||
---
|
||||
include/linux/phy.h | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
--- a/include/linux/phy.h
|
||||
+++ b/include/linux/phy.h
|
||||
@@ -152,6 +152,7 @@ typedef enum {
|
||||
PHY_INTERFACE_MODE_USXGMII,
|
||||
/* 10GBASE-KR - with Clause 73 AN */
|
||||
PHY_INTERFACE_MODE_10GKR,
|
||||
+ PHY_INTERFACE_MODE_2500SGMII,
|
||||
PHY_INTERFACE_MODE_MAX,
|
||||
} phy_interface_t;
|
||||
|
||||
@@ -267,6 +268,8 @@ static inline const char *phy_modes(phy_
|
||||
return "10gbase-kr";
|
||||
case PHY_INTERFACE_MODE_100BASEX:
|
||||
return "100base-x";
|
||||
+ case PHY_INTERFACE_MODE_2500SGMII:
|
||||
+ return "sgmii-2500";
|
||||
default:
|
||||
return "unknown";
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user