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realtek: restructure Zyxel XGS1210-12 device tree files
This is a preparation for adding support for XGS1010-12, which is almost identical to XGS1210-12, with some small differences (partition layout, missing reset key). In addition to moving the common parts to a new file, also simplify the definition of the 2.5G PHYs to reduce duplication. With this change, the revision-specific files only have to specify the SMI addresses. Signed-off-by: Jan Hoffmann <jan@3e8.eu> Link: https://github.com/openwrt/openwrt/pull/20469 Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Jan Hoffmann
Robert Marko
parent
3570dee5f0
commit
67b687af91
@ -8,41 +8,10 @@
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model = "Zyxel XGS1210-12 A1 Switch";
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};
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&mdio_bus0 {
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phy24: ethernet-phy@24 {
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reg = <24>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 8>;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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phy25: ethernet-phy@25 {
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reg = <25>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <2 9>;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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&phy24 {
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rtl9300,smi-address = <1 8>;
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};
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&switch0 {
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ports {
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port@24 {
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reg = <24>;
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label = "lan9";
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pcs-handle = <&serdes6>;
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phy-handle = <&phy24>;
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phy-mode = "2500base-x";
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led-set = <1>;
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};
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port@25 {
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reg = <25>;
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label = "lan10";
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pcs-handle = <&serdes7>;
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phy-handle = <&phy25>;
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phy-mode = "2500base-x";
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led-set = <1>;
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};
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};
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&phy25 {
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rtl9300,smi-address = <2 9>;
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};
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@ -8,41 +8,10 @@
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model = "Zyxel XGS1210-12 B1 Switch";
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};
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&mdio_bus0 {
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phy24: ethernet-phy@24 {
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reg = <24>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <1 1>;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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phy25: ethernet-phy@25 {
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reg = <25>;
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compatible = "ethernet-phy-ieee802.3-c45";
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rtl9300,smi-address = <2 2>;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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&phy24 {
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rtl9300,smi-address = <1 1>;
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};
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&switch0 {
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ports {
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port@24 {
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reg = <24>;
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label = "lan9";
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pcs-handle = <&serdes6>;
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phy-handle = <&phy24>;
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phy-mode = "2500base-x";
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led-set = <1>;
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};
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port@25 {
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reg = <25>;
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label = "lan10";
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pcs-handle = <&serdes7>;
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phy-handle = <&phy25>;
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phy-mode = "2500base-x";
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led-set = <1>;
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};
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};
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&phy25 {
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rtl9300,smi-address = <2 2>;
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};
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@ -1,21 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "rtl9302_zyxel_xgs1x10-12-common.dtsi"
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/ {
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aliases {
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led-boot = &led_pwr_sys;
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led-failsafe = &led_pwr_sys;
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led-running = &led_pwr_sys;
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led-upgrade = &led_pwr_sys;
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};
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keys {
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compatible = "gpio-keys";
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@ -25,76 +13,6 @@
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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led_pwr_sys: led-0 {
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label = "green:power";
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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};
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};
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sfp0: sfp-p11 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
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};
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sfp1: sfp-p12 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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};
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led_set: led_set {
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compatible = "realtek,rtl9300-leds";
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active-low;
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// LED set 0:
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// Amber: 100M/10M
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// Yellow: 1G
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led_set0 = <0x0a20 0x0b80>;
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// LED set 1:
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// Blue: 2.5G
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// Green: 2.5G
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// Yellow: 1G
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// Amber: 100M/10M
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// (Blue + Green = Cyan)
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led_set1 = <0x0b80 0x0a20 0x0a08 0x0a08>;
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// LED set 2:
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// Blue: 10G/5G/2.5G
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// Yellow: 5G/2.5G/1G
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// (Blue + Yellow = Purple)
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led_set2 = <0x0a2a 0x0a0b>;
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};
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};
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&i2c_mst1 {
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status = "okay";
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/* i2c of the left SFP+ cage seen from the front; port 11 */
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i2c0: i2c@0 {
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reg = <0>;
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};
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/* i2c of the right SFP+ cage seen from the front; port 12 */
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i2c1: i2c@1 {
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reg = <1>;
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};
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};
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&spi0 {
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@ -145,151 +63,3 @@
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};
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};
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};
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&mdio_bus0 {
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/* External RTL8218D PHY */
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phy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 0>;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 2>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 3>;
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 4>;
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 5>;
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};
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phy6: ethernet-phy@6 {
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reg = <6>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 6>;
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};
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phy7: ethernet-phy@7 {
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reg = <7>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 7>;
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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pcs-handle = <&serdes2>;
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phy-handle = <&phy0>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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pcs-handle = <&serdes2>;
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phy-handle = <&phy1>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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pcs-handle = <&serdes2>;
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phy-handle = <&phy2>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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pcs-handle = <&serdes2>;
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phy-handle = <&phy3>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@4 {
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reg = <4>;
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label = "lan5";
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pcs-handle = <&serdes2>;
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phy-handle = <&phy4>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@5 {
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reg = <5>;
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label = "lan6";
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pcs-handle = <&serdes2>;
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phy-handle = <&phy5>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@6 {
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reg = <6>;
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label = "lan7";
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pcs-handle = <&serdes2>;
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phy-handle = <&phy6>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@7 {
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reg = <7>;
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label = "lan8";
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pcs-handle = <&serdes2>;
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phy-handle = <&phy7>;
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phy-mode = "usxgmii";
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led-set = <0>;
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};
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port@26 {
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reg = <26>;
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label = "lan11";
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pcs-handle = <&serdes8>;
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phy-mode = "1000base-x";
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sfp = <&sfp0>;
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led-set = <2>;
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managed = "in-band-status";
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};
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port@27 {
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reg = <27>;
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label = "lan12";
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pcs-handle = <&serdes9>;
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phy-mode = "1000base-x";
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sfp = <&sfp1>;
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led-set = <2>;
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managed = "in-band-status";
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <10000>;
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full-duplex;
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};
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};
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};
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};
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266
target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi
Normal file
266
target/linux/realtek/dts/rtl9302_zyxel_xgs1x10-12-common.dtsi
Normal file
@ -0,0 +1,266 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl930x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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/ {
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aliases {
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led-boot = &led_pwr_sys;
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led-failsafe = &led_pwr_sys;
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led-running = &led_pwr_sys;
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led-upgrade = &led_pwr_sys;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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led_pwr_sys: led-0 {
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label = "green:power";
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
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};
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};
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sfp0: sfp-p11 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
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};
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sfp1: sfp-p12 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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};
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led_set: led_set {
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compatible = "realtek,rtl9300-leds";
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active-low;
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// LED set 0:
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// Amber: 100M/10M
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// Yellow: 1G
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led_set0 = <0x0a20 0x0b80>;
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// LED set 1:
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// Blue: 2.5G
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// Green: 2.5G
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// Yellow: 1G
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// Amber: 100M/10M
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// (Blue + Green = Cyan)
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led_set1 = <0x0b80 0x0a20 0x0a08 0x0a08>;
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// LED set 2:
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// Blue: 10G/5G/2.5G
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// Yellow: 5G/2.5G/1G
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// (Blue + Yellow = Purple)
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led_set2 = <0x0a2a 0x0a0b>;
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};
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};
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&i2c_mst1 {
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status = "okay";
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/* i2c of the left SFP+ cage seen from the front; port 11 */
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i2c0: i2c@0 {
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reg = <0>;
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};
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/* i2c of the right SFP+ cage seen from the front; port 12 */
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i2c1: i2c@1 {
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reg = <1>;
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};
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};
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&mdio_bus0 {
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/* External RTL8218D PHY */
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phy0: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 0>;
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// Disabled because we do not know how to bring up again
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// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 2>;
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 3>;
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 4>;
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};
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 5>;
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};
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phy6: ethernet-phy@6 {
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reg = <6>;
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compatible = "ethernet-phy-ieee802.3-c22";
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rtl9300,smi-address = <0 6>;
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};
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phy7: ethernet-phy@7 {
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reg = <7>;
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compatible = "ethernet-phy-ieee802.3-c22";
|
||||
rtl9300,smi-address = <0 7>;
|
||||
};
|
||||
|
||||
phy24: ethernet-phy@24 {
|
||||
reg = <24>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
// Disabled because we do not know how to bring up again
|
||||
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
phy25: ethernet-phy@25 {
|
||||
reg = <25>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
// Disabled because we do not know how to bring up again
|
||||
// reset-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan1";
|
||||
pcs-handle = <&serdes2>;
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "usxgmii";
|
||||
led-set = <0>;
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
pcs-handle = <&serdes2>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "usxgmii";
|
||||
led-set = <0>;
|
||||
};
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
pcs-handle = <&serdes2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-mode = "usxgmii";
|
||||
led-set = <0>;
|
||||
};
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
pcs-handle = <&serdes2>;
|
||||
phy-handle = <&phy3>;
|
||||
phy-mode = "usxgmii";
|
||||
led-set = <0>;
|
||||
};
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan5";
|
||||
pcs-handle = <&serdes2>;
|
||||
phy-handle = <&phy4>;
|
||||
phy-mode = "usxgmii";
|
||||
led-set = <0>;
|
||||
};
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "lan6";
|
||||
pcs-handle = <&serdes2>;
|
||||
phy-handle = <&phy5>;
|
||||
phy-mode = "usxgmii";
|
||||
led-set = <0>;
|
||||
};
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
label = "lan7";
|
||||
pcs-handle = <&serdes2>;
|
||||
phy-handle = <&phy6>;
|
||||
phy-mode = "usxgmii";
|
||||
led-set = <0>;
|
||||
};
|
||||
port@7 {
|
||||
reg = <7>;
|
||||
label = "lan8";
|
||||
pcs-handle = <&serdes2>;
|
||||
phy-handle = <&phy7>;
|
||||
phy-mode = "usxgmii";
|
||||
led-set = <0>;
|
||||
};
|
||||
|
||||
port@24 {
|
||||
reg = <24>;
|
||||
label = "lan9";
|
||||
pcs-handle = <&serdes6>;
|
||||
phy-handle = <&phy24>;
|
||||
phy-mode = "2500base-x";
|
||||
led-set = <1>;
|
||||
};
|
||||
port@25 {
|
||||
reg = <25>;
|
||||
label = "lan10";
|
||||
pcs-handle = <&serdes7>;
|
||||
phy-handle = <&phy25>;
|
||||
phy-mode = "2500base-x";
|
||||
led-set = <1>;
|
||||
};
|
||||
|
||||
port@26 {
|
||||
reg = <26>;
|
||||
label = "lan11";
|
||||
pcs-handle = <&serdes8>;
|
||||
phy-mode = "1000base-x";
|
||||
sfp = <&sfp0>;
|
||||
led-set = <2>;
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@27 {
|
||||
reg = <27>;
|
||||
label = "lan12";
|
||||
pcs-handle = <&serdes9>;
|
||||
phy-mode = "1000base-x";
|
||||
sfp = <&sfp1>;
|
||||
led-set = <2>;
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@28 {
|
||||
ethernet = <ðernet0>;
|
||||
reg = <28>;
|
||||
phy-mode = "internal";
|
||||
fixed-link {
|
||||
speed = <10000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user