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rockchip: backport MMC CQE fixes
Added missing platform data struct for RK3576 to fix boot issues, fixed general stability issues and also improved random write performance. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/21028 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Tianling Shen
Hauke Mehrtens
parent
5aeaddc0c8
commit
4582d25a66
@ -0,0 +1,55 @@
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From 69cc9d4075855661268327c38c9b0e71ac37eb1c Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Fri, 21 Nov 2025 17:26:59 +0100
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Subject: [PATCH] mmc: sdhci-of-dwcmshc: Fix command queue support for RK3576
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When I added command queue engine (CQE) support for the Rockchip eMMC
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controller, I missed that RK3576 has a separate platform data struct.
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While things are working fine on RK3588 (I tested the ROCK 5B) and
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the suspend issue is fixed on the RK3576 (I tested the Sige5), this
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results in stability issues. By also adding the necessary hooks for
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the RK3576 platform the following problems can be avoided:
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[ 15.606895] mmc0: running CQE recovery
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[ 15.616189] mmc0: running CQE recovery
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[...]
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[ 25.911484] mmc0: running CQE recovery
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[ 25.926305] mmc0: running CQE recovery
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[ 25.927468] mmc0: running CQE recovery
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[...]
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[ 26.255719] mmc0: running CQE recovery
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[ 26.257162] ------------[ cut here ]------------
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[ 26.257581] mmc0: cqhci: spurious TCN for tag 31
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[ 26.258034] WARNING: CPU: 0 PID: 0 at drivers/mmc/host/cqhci-core.c:796 cqhci_irq+0x440/0x68c
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[ 26.263786] CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Not tainted 6.18.0-rc6-gd984ebbf0d15 #1 PREEMPT
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[ 26.264561] Hardware name: ArmSoM Sige5 (DT)
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[...]
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[ 26.272748] Call trace:
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[ 26.272964] cqhci_irq+0x440/0x68c (P)
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[ 26.273296] dwcmshc_cqe_irq_handler+0x54/0x88
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[ 26.273689] sdhci_irq+0xbc/0x1200
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[ 26.273991] __handle_irq_event_percpu+0x54/0x1d0
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[...]
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Note that the above problems do not necessarily happen with every boot.
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Reported-by: Adrian Hunter <adrian.hunter@intel.com>
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Closes: https://lore.kernel.org/linux-rockchip/01949bc9-4873-498b-ac7d-f008393ccc4c@intel.com/
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Fixes: fda1e0af7c28f ("mmc: sdhci-of-dwcmshc: Add command queue support for rockchip SOCs")
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/sdhci-of-dwcmshc.c | 1 +
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1 file changed, 1 insertion(+)
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--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
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+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
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@@ -1333,6 +1333,7 @@ static const struct dwcmshc_pltfm_data s
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
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SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN,
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},
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+ .cqhci_host_ops = &rk35xx_cqhci_ops,
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.init = dwcmshc_rk35xx_init,
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.postinit = dwcmshc_rk3576_postinit,
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};
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@ -0,0 +1,42 @@
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From c7ce6453b769c45006ed4983762f81e130878171 Mon Sep 17 00:00:00 2001
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From: Shawn Lin <shawn.lin@rock-chips.com>
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Date: Wed, 26 Nov 2025 07:26:39 +0800
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Subject: [PATCH] mmc: sdhci-of-dwcmshc: Disable internal clock auto gate for
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Rockchip SOCs
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Enabling CMDQ support can lead to random occurrences of the error log when
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there are RPMB access and data flush executed:
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"mmc2: Timeout waiting for hardware interrupt."
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Enabling CMDQ and then issuing a DCMD as the final command before disabling
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it causes the eMMC controller to auto-gate its internal clock. Chip simulation
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shows this results in a state machine mismatch after CMDQ mode exit, triggering
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data-timeout errors for all subsequent read and write operations.
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Therefore, the auto-clock-gate function must be disabled whenever CMDQ is
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enabled.
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Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
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Acked-by: Adrian Hunter <adrian.hunter@intel.com>
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Fixes: fda1e0af7c28 ("mmc: sdhci-of-dwcmshc: Add command queue support for rockchip SOCs")
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/sdhci-of-dwcmshc.c | 3 ++-
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1 file changed, 2 insertions(+), 1 deletion(-)
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--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
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+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
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@@ -696,10 +696,11 @@ static void dwcmshc_rk3568_set_clock(str
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sdhci_set_clock(host, clock);
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- /* Disable cmd conflict check */
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+ /* Disable cmd conflict check and internal clock gate */
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reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3;
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extra = sdhci_readl(host, reg);
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extra &= ~BIT(0);
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+ extra |= BIT(4);
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sdhci_writel(host, extra, reg);
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if (clock <= 52000000) {
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@ -0,0 +1,44 @@
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From 79cf71c0b177c0e23d411e2469435e2c2f83f563 Mon Sep 17 00:00:00 2001
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From: Shawn Lin <shawn.lin@rock-chips.com>
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Date: Wed, 26 Nov 2025 07:26:40 +0800
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Subject: [PATCH] mmc: sdhci-of-dwcmshc: reduce CIT for better performance
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CQHCI_SSC1.CIT indicates to the CQE the polling period to use for
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periodic SEND_QUEUE_STATUS (CMD13) polling. Some eMMCs have only one
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hardware queue, and CMD13 can only query one slot at a time for data
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transmission, which cannot be processed in parallel. Modifying the
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CMD13 query interval can increase the query frequency and improve
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random write performance.
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Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
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Acked-by: Adrian Hunter <adrian.hunter@intel.com>
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/cqhci.h | 1 +
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drivers/mmc/host/sdhci-of-dwcmshc.c | 5 +++++
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2 files changed, 6 insertions(+)
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--- a/drivers/mmc/host/cqhci.h
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+++ b/drivers/mmc/host/cqhci.h
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@@ -93,6 +93,7 @@
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/* send status config 1 */
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#define CQHCI_SSC1 0x40
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#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16)
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+#define CQHCI_SSC1_CIT_MASK GENMASK(15, 0)
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/* send status config 2 */
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#define CQHCI_SSC2 0x44
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--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
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+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
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@@ -614,6 +614,11 @@ static void rk35xx_sdhci_cqe_pre_enable(
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struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host);
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u32 reg;
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+ /* Set Send Status Command Idle Timer to 10.66us (256 * 1 / 24) */
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+ reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
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+ reg = (reg & ~CQHCI_SSC1_CIT_MASK) | 0x0100;
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+ sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_SSC1);
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+
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reg = sdhci_readl(host, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
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reg |= CQHCI_ENABLE;
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sdhci_writel(host, reg, dwc_priv->vendor_specific_area2 + CQHCI_CFG);
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