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realtek: Clean up global array definitions

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Global array initialization must have the open brace on the first
line and the next lines must be intended by one level. The closing
brace must be one a separate line.

Signed-off-by: Sven Eckelmann <sven@narfation.org>
Link: https://github.com/openwrt/openwrt/pull/20906
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Sven Eckelmann 2025-11-23 16:50:29 +01:00 committed by Hauke Mehrtens
parent 8f42966c08
commit 230a1835c3
6 changed files with 27 additions and 24 deletions
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23
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c
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@ -7,14 +7,21 @@
#include "rtl83xx.h"
static const u8 ipv4_ll_mcast_addr_base[ETH_ALEN] =
{ 0x01, 0x00, 0x5e, 0x00, 0x00, 0x00 };
static const u8 ipv4_ll_mcast_addr_mask[ETH_ALEN] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
static const u8 ipv6_all_hosts_mcast_addr_base[ETH_ALEN] =
{ 0x33, 0x33, 0x00, 0x00, 0x00, 0x01 };
static const u8 ipv6_all_hosts_mcast_addr_mask[ETH_ALEN] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
static const u8 ipv4_ll_mcast_addr_base[ETH_ALEN] = {
0x01, 0x00, 0x5e, 0x00, 0x00, 0x00
};
static const u8 ipv4_ll_mcast_addr_mask[ETH_ALEN] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0x00
};
static const u8 ipv6_all_hosts_mcast_addr_base[ETH_ALEN] = {
0x33, 0x33, 0x00, 0x00, 0x00, 0x01
};
static const u8 ipv6_all_hosts_mcast_addr_mask[ETH_ALEN] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff
};
static void rtldsa_init_counters(struct rtl838x_switch_priv *priv);
static void rtldsa_port_xstp_state_set(struct rtl838x_switch_priv *priv, int port,

4
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c
View File

@ -82,8 +82,8 @@ enum template_field_id {
* TODO: See all src/app/diag_v2/src/diag_pie.c
*/
#define N_FIXED_TEMPLATES 5
static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
{
static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = {
{
TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_OTAG,
TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,

4
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c
View File

@ -88,8 +88,8 @@ enum template_field_id {
/* Number of fixed templates predefined in the SoC */
#define N_FIXED_TEMPLATES 5
static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
{
static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = {
{
TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_ITAG,
TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,

4
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c
View File

@ -95,8 +95,8 @@ enum template_field_id {
/* Number of fixed templates predefined in the RTL9300 SoC */
#define N_FIXED_TEMPLATES 5
/* RTL9300 specific predefined templates */
static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
{
static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = {
{
TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,

4
target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c
View File

@ -81,8 +81,8 @@ enum template_field_id {
/* Number of fixed templates predefined in the RTL9300 SoC */
#define N_FIXED_TEMPLATES 5
/* RTL931x specific predefined templates */
static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS_RTL931X] =
{
static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS_RTL931X] = {
{
TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,

12
target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c
View File

@ -1642,8 +1642,7 @@ static int rtpcs_930x_sds_set_polarity(struct rtpcs_ctrl *ctrl, u32 sds,
return rtpcs_sds_write_bits(ctrl, sds, 0x0, 0x0, 9, 8, val);
}
static const sds_config rtpcs_930x_sds_cfg_10gr_even[] =
{
static const sds_config rtpcs_930x_sds_cfg_10gr_even[] = {
/* 1G */
{0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
{0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
@ -1690,8 +1689,7 @@ static const sds_config rtpcs_930x_sds_cfg_10gr_even[] =
{0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
};
static const sds_config rtpcs_930x_sds_cfg_10gr_odd[] =
{
static const sds_config rtpcs_930x_sds_cfg_10gr_odd[] = {
/* 1G */
{0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
{0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
@ -1733,8 +1731,7 @@ static const sds_config rtpcs_930x_sds_cfg_10gr_odd[] =
{0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
};
static const sds_config rtpcs_930x_sds_cfg_10g_2500bx_even[] =
{
static const sds_config rtpcs_930x_sds_cfg_10g_2500bx_even[] = {
{0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100},
{0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
{0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008},
@ -1756,8 +1753,7 @@ static const sds_config rtpcs_930x_sds_cfg_10g_2500bx_even[] =
{0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x66E1},
};
static const sds_config rtpcs_930x_sds_cfg_10g_2500bx_odd[] =
{
static const sds_config rtpcs_930x_sds_cfg_10g_2500bx_odd[] = {
{0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100},
{0x21, 0x03, 0x8206}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
{0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},