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mediatek: fix uart clocks in MT7987 infracfg clock driver

Browse Source 
MediaTek has applied a fix for the MT7987 infracfg clock driver in their
SDK, pick it.

Link: fe98d04c60/master/files/target/linux/mediatek/patches-6.12/999-clk-01-clk-mediatek-fix-mt7987-infracfg-clk-driver.patch
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle 2025-11-18 11:17:39 +00:00
parent 93cfbc7d1f
commit 1c3b32c45a
1 changed files with 1 additions and 4 deletions
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5
target/linux/mediatek/patches-6.12/361-clk-mediatek-add-mt7987-clock-drivers-support.patch
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@ -273,7 +273,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+MODULE_LICENSE("GPL");
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7987-infracfg.c
@@ -0,0 +1,328 @@
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 MediaTek Inc.
@ -301,15 +301,12 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+static DEFINE_SPINLOCK(mt7987_clk_lock);
+
+static const char *const infra_mux_uart0_parents[] = { "csw_infra_f26m_sel",
+ "infra_hf_66m_uart0_pck",
+ "uart_sel" };
+
+static const char *const infra_mux_uart1_parents[] = { "csw_infra_f26m_sel",
+ "infra_hf_66m_uart1_pck",
+ "uart_sel" };
+
+static const char *const infra_mux_uart2_parents[] = { "csw_infra_f26m_sel",
+ "infra_hf_66m_uart1_pck",
+ "uart_sel" };
+
+static const char *const infra_mux_spi0_parents[] = {