// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include "mt7620a.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/mtd/partitions/uimage.h>

/ {
	compatible = "ralink,mt7620a-soc";

	aliases {
		led-boot = &led_power;
		led-failsafe = &led_power;
		led-running = &led_power;
		led-upgrade = &led_power;
	};

	keys {
		compatible = "gpio-keys";

		reset_wps {
			label = "reset_wps";
			gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led_power: power {
			function = LED_FUNCTION_POWER;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
		};

		lan {
			function = LED_FUNCTION_LAN;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
		};

		wps {
			function = LED_FUNCTION_WPS;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
		};
	};
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&spi0 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x30000>;
				read-only;
			};

			partition@30000 {
				label = "u-boot-env";
				reg = <0x30000 0x10000>;
				read-only;
			};

			partition@40000 {
				label = "factory";
				reg = <0x40000 0x10000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					eeprom_factory_0: eeprom@0 {
						reg = <0x0 0x200>;
					};

					eeprom_factory_8000: eeprom@8000 {
						reg = <0x8000 0x200>;
					};

					macaddr_factory_4: macaddr@4 {
						compatible = "mac-base";
						reg = <0x4 0x6>;
						#nvmem-cell-cells = <1>;
					};
				};
			};

			partition@50000 {
				label = "cimage";
				reg = <0x50000 0x20000>;
				read-only;
			};

			partition@70000 {
				compatible = "openwrt,uimage", "denx,uimage";
				openwrt,offset = <FW_EDIMAX_OFFSET>;
				openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
				label = "firmware";
				reg = <0x00070000 0x00790000>;
			};
		};
	};
};

&state_default {
	gpio {
		groups = "i2c", "uartf", "nd_sd", "rgmii2";
		function = "gpio";
	};
};

&pinctrl {
	phy_reset_pins: phy-reset {
		gpio {
			groups = "spi refclk";
			function = "gpio";
		};
	};
};

&ethernet {
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii1_pins &mdio_pins &phy_reset_pins>;

	nvmem-cells = <&macaddr_factory_4 0>;
	nvmem-cell-names = "mac-address";

	phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <30>;

	port@5 {
		status = "okay";
		mediatek,fixed-link = <1000 1 1 1>;
		phy-mode = "rgmii";
	};

	mdio-bus {
		status = "okay";

		phy0: ethernet-phy@0 {
			status = "disabled";
			reg = <0>;
			phy-mode = "rgmii";
		};

		phy1: ethernet-phy@1 {
			status = "disabled";
			reg = <1>;
			phy-mode = "rgmii";
		};

		phy2: ethernet-phy@2 {
			status = "disabled";
			reg = <2>;
			phy-mode = "rgmii";
		};

		phy3: ethernet-phy@3 {
			status = "disabled";
			reg = <3>;
			phy-mode = "rgmii";
		};

		phy4: ethernet-phy@4 {
			status = "disabled";
			reg = <4>;
			phy-mode = "rgmii";
		};
	};
};

&gsw {
	mediatek,ephy-base = /bits/ 8 <8>;
};

&wmac {
	nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_4 0>;
	nvmem-cell-names = "eeprom", "mac-address";
};

&pcie {
	status = "okay";
};

&pcie0 {
	wifi@0,0 {
		reg = <0x0000 0 0 0 0>;
		ieee80211-freq-limit = <5000000 6000000>;
		nvmem-cells = <&eeprom_factory_8000>, <&macaddr_factory_4 2>;
		nvmem-cell-names = "eeprom", "mac-address";
	};
};
